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Scholar
Scholar
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Registered: ‎08-07-2014

Regarding the VTPG v7.0

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I am referring to the VTPG v7.0 PG103, April05, 2017. At page 14, the AXI4_Lite control interface is described and the signals are tabulated.

1. There is a typo at the 2nd row of this table. The s_axi_CTRL_awread should be s_axi_CTRL_awready.

2. I don't see the the *_wstrb signal in this table. But the *_wstrb signal is depicted at page 9, fig 2-1.

Now if I refer to the Xilinx Video Beginner Series 4 Tutorial and run the simulation, then I see the Xilinx AXI VIP driving the *_wstrb.

My question is, is it necessary to drive the *_wstrb signal for configuring the VTPG?

@florentw 

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Registered: ‎11-09-2015

Hi @dpaul24 


@dpaul24 wrote:

I am referring to the VTPG v7.0 PG103, April05, 2017. At page 14, the AXI4_Lite control interface is described and the signals are tabulated.

1. There is a typo at the 2nd row of this table. The s_axi_CTRL_awread should be s_axi_CTRL_awready.

[Florent] - This is fixed in the latest version of the doc (Video Test Pattern Generator v8.0 - PG103 December 17, 2019), Xilinx is not updating the previous versions of a doc.

2. I don't see the the *_wstrb signal in this table. But the *_wstrb signal is depicted at page 9, fig 2-1.

Now if I refer to the Xilinx Video Beginner Series 4 Tutorial and run the simulation, then I see the Xilinx AXI VIP driving the *_wstrb.

My question is, is it necessary to drive the *_wstrb signal for configuring the VTPG?


[Florent] - No this is not required. This is coming from the fact that the TPG is a HLS based IP. When an AXI4 interface is implemented using HLS, all the signals will be implemented even the one which are optional. In the AXi4-Stream spec, the wstrb signal is an optional signal.

The test pattern generator uses the AXI4-Stream as defined in UG934, which is kind of the Xilinx spec for AXI4-Stream interfaces for Xilinx Video IPs. All the Xilinx Video IPs follow this guide to ensure inter-compatibility. The WSTRB is not used by any Xilinx video IPs. So you can leave it unconnected or connected all bit to 1.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Hi @dpaul24 


@dpaul24 wrote:

I am referring to the VTPG v7.0 PG103, April05, 2017. At page 14, the AXI4_Lite control interface is described and the signals are tabulated.

1. There is a typo at the 2nd row of this table. The s_axi_CTRL_awread should be s_axi_CTRL_awready.

[Florent] - This is fixed in the latest version of the doc (Video Test Pattern Generator v8.0 - PG103 December 17, 2019), Xilinx is not updating the previous versions of a doc.

2. I don't see the the *_wstrb signal in this table. But the *_wstrb signal is depicted at page 9, fig 2-1.

Now if I refer to the Xilinx Video Beginner Series 4 Tutorial and run the simulation, then I see the Xilinx AXI VIP driving the *_wstrb.

My question is, is it necessary to drive the *_wstrb signal for configuring the VTPG?


[Florent] - No this is not required. This is coming from the fact that the TPG is a HLS based IP. When an AXI4 interface is implemented using HLS, all the signals will be implemented even the one which are optional. In the AXi4-Stream spec, the wstrb signal is an optional signal.

The test pattern generator uses the AXI4-Stream as defined in UG934, which is kind of the Xilinx spec for AXI4-Stream interfaces for Xilinx Video IPs. All the Xilinx Video IPs follow this guide to ensure inter-compatibility. The WSTRB is not used by any Xilinx video IPs. So you can leave it unconnected or connected all bit to 1.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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