04-10-2021 02:50 AM
I have a Digilent Genesys 2 board and wanted to use the Display port Sink and Source available on board. The DP hardware is similar to what we have on Inrevium TB-FMCH-DP, the required FMC card to test the Xilinx DisplayPort IP. This IP was available in older Vivado versions (Pre 2016.4).
I have Vivado 2018.2 and on this version, we get two separate IPs for the DisplayPort RX subsystem and DisplayPort TX subsystem. I have generated the available passthrough without HDCP example (for KC705) and have gone through the block design and MicroBlaze firmware.
Problem is that this example design expects the use of a newer DisplayPort FMC card TB-FMCH-DP3 which contains Retimer and Redriver ICs between FPGA and the DP connectors. On studying the DisplayPort RX subsystem IP product guide, I see that this IP expects the presence of DP159 Retimer IC.
Now my goal is to make all the required changes in the Vivado block design and MicroBlaze firmware to make this work on the Genesys 2 board. I was hoping that when using slower link rates supported in DisplayPort standard version 1.1, the absence of DP159 will not be an issue. I do want to mention that I don't have any in-depth knowledge of the DisplayPort standard.
Genesys 2 board has a fixed 135 MHz MGTREFCLK available which I can use for both RX and TX channels. I can set link rates to 2.7 Gbps which is supported on Genesys 2 board. I will have to make board-related changes like changing DDR3, UART pins, and the rest of the XDC. I will have to make changes in firmware to skip all the steps involving DP159.
Now I have already spent 1 and a half week on all this and moving forward I wanted to ask the experts here whether what I am planning to do is:
a) Possible but tricky and difficult
b) Shouldn't be a problem
c) absolutely absurd
Your insight will be very valuable for me
Thanks in advance
04-11-2021 02:45 PM
It depends on your acknowledgement for display and Xilinx's DP IP.
So, my answer is a) or b).
If you have DP protocol anaylzer and/or high speed oscilloscope to make sure signal integrity on DP signals, my answe is b.
Hope this helps.
04-12-2021 06:27 AM
This might work in some cases but might also fail.
Xilinx only Displayport 1.2 solutions are using the DP159 retimer (and redriver for TX). Even with the "old" displayport IP, it was using the TB-FMCH-DP3 FMC card (thus retimer) in the last version.
This is only with the retimer that Xilinx solution is passing the Displayport 1.2 compliance test.
I believe the TB-FMCH-DP was used for DP1.1. But I do not remember if Xilinx was going through the compliance test. So basically it might work with some sources/sinks but it might also not work with other sink/sources/cables.
Also, because the IP expects the DP159, you might need to edit the driver to make it work.
So in conclusion: This will require quite a lot of work and you are not sure that it will work with your source and sink. And for this development, you will get no support from Xilinx.
Hope that gives you some answers to decide if you want to go ahead with it