We want to implement SDI design using vivado 2020.1 by including the GT Common in the Example Design using Zynq UltraScale+ MPSoC custom board with 19EG device and have encountered following issues.
1. Include GT Common in Example Design option appears for USD SDI GT IP only in vivado 2019.2 it is not available in 2020.1.
2. Even in 2019.2 there is no proper PG for USD SDI GT IP, when we include GT common in example design IP shows some of the ports but there is no proper description of these ports in PG380 and not even in UG576.
Actually we want to implement GT Common in Example design because the GTH quad is shared among another protocol which uses a different reference clock.
Someone Please Guide us how we can start with the design as there no proper documentation and resources for this purpose.
I also want to know whether we can achieve this using block design or should we go for IP Integrator design using Ultrascale Transceiver Wizard ?