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francocapraro12
Adventurer
Adventurer
312 Views
Registered: ‎09-27-2018

SDI TX Subsystem not respond

Hello, Im using a Ultrazed EV SOM + CC. Im trying to implement the SDI TX side. My part of problem is the SDI-TX IP core:

francocapraro12_3-1622528576518.png

 

 

I trying to configure the  IP in vitis but i cannot see any changes with ILA:

francocapraro12_0-1622528025043.png

My code :

xil_printf("SDI TX Subsystem self test example\n\r");
	xil_printf("---------------------------------\n\r\n\r");

	Status = SdiTxSs_SelfTestExample(XV_SDITXSS_DEVICE_ID);
	if (Status != XST_SUCCESS) {
		xil_printf("SDI TX Subsystem self test example "
			"failed\n\r");
		return XST_FAILURE;
	}

	xil_printf("/* Initialize SDI TX Subsystem */\n\r");
	XV_SdiTxSs_ConfigPtr = XV_SdiTxSs_LookupConfig(XPAR_XV_SDITXSS_0_DEVICE_ID);

	XV_SdiTxSs_ConfigPtr->BaseAddress = XPAR_XV_SDITXSS_0_BASEADDR;
	if (!XV_SdiTxSs_ConfigPtr) {
		SdiTxSs.IsReady = 0;
		return XST_DEVICE_NOT_FOUND;
	}
	Status = XV_SdiTxSs_CfgInitialize(&SdiTxSs,
				XV_SdiTxSs_ConfigPtr,
				XV_SdiTxSs_ConfigPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		xil_printf("ERR:: SDI TX Initialization failed %d\r\n", Status);
		return XST_FAILURE;
	}
	XVidC_VideoStream *SdiTxSsVidStreamPtr;
	XSdiVid_Transport *SdiTxSsTransportPtr;

	SdiTxSsVidStreamPtr = XV_SdiTxSs_GetVideoStream(&SdiTxSs, 0);
	SdiTxSsTransportPtr = XV_SdiTxSs_GetTransport(&SdiTxSs);

	xil_printf("set default resolution XVIDC_VM_1920x1080\n\r");
	XVidC_SetVideoStream(SdiTxSsVidStreamPtr,XVIDC_VM_1920x1080_30_P , XVIDC_CSF_YCRCB_444,XVIDC_BPC_8,XVIDC_PPC_2);
	SdiTxSsTransportPtr->ActiveStreams = 8;
	SdiTxSsTransportPtr->IsFractional = 0;
	SdiTxSsTransportPtr->IsLevelB3G = 0;
	//SdiTxSsTransportPtr->TFamily = 3;
	SdiTxSsTransportPtr->TMode = 5;
	XV_SdiTxSs_StreamConfig(&SdiTxSs);

 

Also i want to say that intf_0_txoutclk is not working.


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2 Replies
florentw
Moderator
Moderator
205 Views
Registered: ‎11-09-2015

HI @francocapraro12 

If intf_0_txoutclk is not working, this is the first thing I would check.

How are you controlling the cmp_gt_ctrl of the UHD-SDI GT IP?

What status are you getting from cmp_gt_sts?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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francocapraro12
Adventurer
Adventurer
195 Views
Registered: ‎09-27-2018

Hi @florentw ,

Yes, im trying to resolve the TXCLKOUT problem. Right now im controlling he cmp_gt_ctrl with a IP (uhdsdi_gt_ctrl.v modified). I did a testbench for this and i get a reset pulse for Bit 0 and 2 of  cmp_gt_ctrl and ALL OTHERS BIT ARE "0":

francocapraro12_0-1623668477357.png

 

francocapraro12_0-1623667159838.png

I can share the IP if you want.

The status in  cmp_gt_sts is  "1" in BIT 6 and 9 all others in "0" (with the IP uhdsdi_gt_ctrl.v NOT working) and then "1" in BIT 9 (with the IP uhdsdi_gt_ctrl.v NOT working, after the reset pulse).

I also tried with sending a  pulse for the PowerDown BITS of both QPLL ( Im using just QPLL0, but i send for both)


I think the problem can be the LOC property of the GTHE4 (i cannot resolve this WARNING at the moment)

francocapraro12_1-1623667262012.png


Thank you for your help,
Franco

 

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