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francocapraro12
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Registered: ‎09-27-2018

SDI Tx / HDMI Rx

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Hello. Im trying to implement a project for ZCU106 with SDI Tx (Output) and HDMI Rx (Input). Can both coexist at the same time ? (because i see Tx/Rx SDI  examples, Rx/Tx HDMI examples in VCU projects, but no crossed each other). If is possible i have some question, please correct me if im wrong:

1) The clock of HDMI Rx will be static at 148.5MHz? so i can set the  SI570 clock to 148.5MHz.

2) Do i need to use NI-DRU ? (becuase it use another clk).

3) The clock of SDI Tx will change to fractional or integer, so i can use the SI5324 clock to the differents values.

My main idea is start with this and work with bare metal, then i will try to add the VCU and create the linux.

Best, 
FC

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nathanx
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Registered: ‎08-01-2007

 

For the "north" and "south" ref clock of GTH, I think the following diagram can answer your question.

nathanx_1-1626074844035.png

 

To answer your questions, 

Q1 -> Do I need use  GTSOUTHREFCLK1 in the IP Core ?

A1 -> Yes, the SOUTHREFCLK is from the above quad, in this case, it's quad 226, since SDI is put on Quad 225. 

Q2 -> If i select GTSOUTHREFCLK0 , will be FMC_HPC0_GBTCLK0_M2C_C? 

A2 -> Yes.

Q3 -> If i select GTNORTHREFCLK1 , will be USER_SMA_MGT_CLOCK_C?

A3 -> Yes.

Q4 -> I cannot select USER_MGT_SI570_CLOCK2_C from Quad 227 to Quad 225 ?

A4 -> No, the number of Quads above the sourcing Quad must not exceed two. So the REFCLK of Quad 227 can be sourced to quad 225.

 

 

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watari
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Registered: ‎06-16-2013

Hi @francocapraro12 

 

>Can both coexist at the same time ?

 

Yes. But you have to use two GTs.

 

>1) The clock of HDMI Rx will be static at 148.5MHz? so i can set the SI570 clock to 148.5MHz.

>2) Do i need to use NI-DRU ? (becuase it use another clk).

>3) The clock of SDI Tx will change to fractional or integer, so i can use the SI5324 clock to the differents values.

 

They are related with what you want to achieve.

What kind of resolution do you want to support ?

 

BTW, would you refer PG236 and PG289 to understand how to implement what you want to achieve, too ?

 

https://www.xilinx.com/support/documentation/ip_documentation/v_hdmi_rx_ss/v3_1/pg236-v-hdmi-rx-ss.pdf

https://www.xilinx.com/support/documentation/ip_documentation/v_smpte_uhdsdi_tx_ss/v2_0/pg289-v-smpte-uhdsdi-tx-ss.pdf

 

Best regards,

 

Best regards,

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francocapraro12
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Hi @watari ,

My resolution will be 1080p (or up to 1080p). Okay i will need to use 2 GT's, but how i  use/configure the clocks to each GT's ?
I'm checking the PG.
Best,
FC 

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watari
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Registered: ‎06-16-2013

Hi @francocapraro12 

 

Would you share your EDID ?

If you only describe detailed video timing in EDID, you don't need NI-DRU.

 

Best regards,

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francocapraro12
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Hi @watari ,
Thank you for answer.
So the EDID is necesary to send the resolution info for the monitor ,right ? (sorry but im newer in the video processing)

if i hold the resolution to 1080p ( i will never change) i dont need NI DRU if my understand is good.
Best ,

FC

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nathanx
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Registered: ‎08-01-2007

Q1: The clock of HDMI Rx will be static at 148.5MHz? so i can set the  SI570 clock to 148.5MHz.

A1: HDMI 2.0 RX required two clocks, one is RX ref clock, which varies based on the resolution and frame rate.

Q2: Do i need to use NI-DRU ? (becuase it use another clk).

A2: If you only need to support 1080p and up to 1080p, the NI-DRU is not required, NI-DRU is used for lower resolutions.

 

Q3: The clock of SDI Tx will change to fractional or integer, so i can use the SI5324 clock to the differents values.

A3: Firstly you should determine the supported resolution, then you can determine the SDI line rate.

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francocapraro12
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Registered: ‎09-27-2018

Hi @nathanx ,

thank you for your answer. I think that im starting with too much requirements. I will reduce the complexity to  just 1080p resolution in for both (SDI Tx in 1080p and HDMI RX in 1080p).
So if i start again:

1) NI-DRU is not required
2) HDMI will use 2 clocks (DRP and RX_Ref ? )
3) SDI will use just 1 clock (integer) of 148.5MHz with SI5324


Best, FC

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watari
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Registered: ‎06-16-2013

Hi @francocapraro12 

 

>So the EDID is necesary to send the resolution info for the monitor ,right ? (sorry but im newer in the video processing)

 

Not need EDID for SDI Tx.

You have to prepare proper EDID for HDMI Rx.

 

>if i hold the resolution to 1080p ( i will never change) i dont need NI DRU if my understand is good.

 

Yes. As @nathanx mentioned details, if your application didn't support under 1080p, ex. 1024x768@60Hz, 800x600@60Hz, 640x480@60Hz and so on, you don't need to use NI-DRU.

 

Best regards,

 

 

nathanx
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Registered: ‎08-01-2007

Not sure your target GT, here is an clocking schme example for HDMI 2.0, since you will use RX only, only the RX ref clock is required for GT. You can also refer to ZCU102/ZCU106 HDMI demo on PG236 chapter 6 - example design.

nathanx_0-1625713073280.png

 

francocapraro12
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Registered: ‎09-27-2018

@watari  and @nathanx . Thank you both for your answers, you really help me. I need to do some test but i think i have the "only 1080p resolution "  working.
My last question (that maybe you understand) is about the "north" and "south"  Clocks Concepts. I saw the GTH documents  (UG576 ) a few times but i couldnt understand pretty well , i will  post the example of SDI Tx Only (https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Video-Blog-Implementing-the-UHD-SDI-TX-subsystem-in-a-TX-only/ba-p/1170471) :
"In general, the reference clock for a Quad (Q(n)) can also be sourced from up to two Quads below (Q(n–1) or Q(n-2)) via GTNORTHREFCLK or from up to two Quads above (Q(n+1) or Q(n+2)) via GTSOUTHREFCLK. For devices that support stacked silicon interconnect (SSI) technology, the reference clock sharing via GTNORTHREFCLK and GTSOUTREFCLK ports is limited within its own super logic
region (SLR)."

Quads In ZCU106:

francocapraro12_0-1625750337903.png

. SDI GT IP Core:

francocapraro12_1-1625751216114.png

 

So:

I need use the Quad 225 for SDI (Tx and Rx  Data Pins) in X0Y8 but if i want to use the USER_MGT_SI570_CLOCK1_CP/N  to generate the clock of 148.5MHz:

1) Do i need use  GTSOUTHREFCLK1 in the IP Core ?

2) If i select GTSOUTHREFCLK0 , will be FMC_HPC0_GBTCLK0_M2C_C? 

3) If i select GTNORTHREFCLK1 , will be USER_SMA_MGT_CLOCK_C?

4) I cannot select USER_MGT_SI570_CLOCK2_C from Quad 227 to Quad 225 ?


Thank you for your time.
FC

 

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nathanx
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Registered: ‎08-01-2007

 

For the "north" and "south" ref clock of GTH, I think the following diagram can answer your question.

nathanx_1-1626074844035.png

 

To answer your questions, 

Q1 -> Do I need use  GTSOUTHREFCLK1 in the IP Core ?

A1 -> Yes, the SOUTHREFCLK is from the above quad, in this case, it's quad 226, since SDI is put on Quad 225. 

Q2 -> If i select GTSOUTHREFCLK0 , will be FMC_HPC0_GBTCLK0_M2C_C? 

A2 -> Yes.

Q3 -> If i select GTNORTHREFCLK1 , will be USER_SMA_MGT_CLOCK_C?

A3 -> Yes.

Q4 -> I cannot select USER_MGT_SI570_CLOCK2_C from Quad 227 to Quad 225 ?

A4 -> No, the number of Quads above the sourcing Quad must not exceed two. So the REFCLK of Quad 227 can be sourced to quad 225.

 

 

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francocapraro12
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Registered: ‎09-27-2018

Hi @nathanx ,

Thank you so much for your help ! Good work !

Best,
FC

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