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Visitor
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Registered: ‎02-08-2018

SDI core - Delay/latency from tx_ds1a/ds2a_in input to tx_txdata output

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Is there a specificied latency from the input of the SDI core (tx_ds1a/ds2a_in) inputs to the output of 20-bit transceiver data?

Looking at the TX block diagram in PG071 (Figure 3-6), there are some registers documented, but there are other blocks such as the LN Insertion, CRC Generate/Insert and SDI Scrambler where I don't know what the latency through those blocks is.

Thank you!

 

 

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Moderator
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Registered: ‎11-09-2015

Hi @dmtutd ,

The same latency should apply for all the 3 rates supported by the IP (SD/HD/3G-SDI). I will update the AR.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
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Registered: ‎02-08-2018

I forgot to add that I've found the documented latency in 3G_SDI mode per the AR below, but wasn't sure if that applied to SDI or HD-SDI mode as well.

 

https://www.xilinx.com/support/answers/70041.html

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @dmtutd ,

The same latency should apply for all the 3 rates supported by the IP (SD/HD/3G-SDI). I will update the AR.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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