08-18-2016 03:51 AM
in our new project we have to integrate an UHD-SDI receiver in a Kintex 7 - 160 device. I have to switch the clock for integer (1.000) order fractional (1.001) signals. How can I switch the QPLL automatical between 148.5MHz and 148.35MHz for the different clocks? I read the XAPP1249 and PG205 but I can't find anything about this.
Thank you for your help.
08-18-2016 03:57 AM
08-18-2016 04:07 AM
but the UHD-SDI core have to change the clock. In XAPP1249 figure 5 there is a signal called QPLLREFCLKSEL. Which module has to set this signal?
08-18-2016 05:16 AM
Yes the cpllrefclksel and qpllrefclksel should be controlled.
In XAPP1249 this is controlled by an dip switch on the board.
Refer to kc705_uhdsdi_demo.v module in the XAPP1249 sources folder to get more details on how this is implemented.
08-18-2016 05:26 AM
my problem is, that in our design I have only the receiver and no dip-switch. I think the receiver should change these signals.
08-18-2016 10:57 PM
I have a big problem that I don't understand the whole documentation about UHD-SDI core. There isn't a practical example, the demo system for kc705 board is impractical. I have to build a UDH-SDI receiver in the FPGA which should support HD-, 3G-, 12G-Standards with 148.5MHz and 148.5MHz/1.001. But there isn't a documentation which is useful. How can I switch between the two ref clocks?
Thank you for your help