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Explorer
Explorer
7,393 Views
Registered: ‎11-25-2014

SMPTE SD/HD/3G-SDI Tx-only

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First some complaints:

 

Why in the world can't this core be generated for Tx-only? This thing is a bear to use, with pieces needed from all over the place. Starting with XAPP592 in my case (Zynq 045), generate the SDI core, generate the GTX transceiver separately, then hack the SDI wrapper from XAPP592 to wire everything up. And for me, where I do not need the Rx path (which includes a ton of extra stuff such as the DRU), there's a lot of hacking required.

 

Life would be a lot easier if the wizard that generates this core allowed customization of what features are needed (which standards (SD/HD/3G), which directions (Rx/Tx), clocking options, etc), then spit out the whole design all wired up inside a wrapper that includes the SDI core, the GTX transceiver, and support logic. The way it works now is almost starting from scratch. XAPP592 helps, but c'mon guys! We're making the transition from HDMI with an external HDMI transmitter. HDMI is a piece of cake compared to this beast and makes me seriously wonder if SDI is worth the hassle.

 

Now my question:

 

If I'm only using the SDI core to transmit can I tie all of the input ports for the receiver side to GND and leave all of the outputs on the receiver side unconnected? Or just leave all of the receiver ports unconnected? Neither PG071 nor XAPP592 addresses the Tx-only case.

 

Thanks.

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Xilinx Employee
Xilinx Employee
13,641 Views
Registered: ‎07-31-2012
If only a receiver or only a transmitter is needed by the application, the input ports for the unused half of the core can be tied to ground and the output ports left unconnected. The synthesis tool will optimize the unused portion of the core out of the application.

This is kind of mentioned in the UG.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

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Explorer
Explorer
7,381 Views
Registered: ‎11-25-2014
I have a related follow-up question. The SDI control module (x7gtx_sdi_control.v included with the XAPP592 reference designs) does not have any input signals or parameters that allow it to be told that the SDI core is Tx-only. So how do I keep it happy in the Tx-only case? Or is the only reasonable way to handle this to make the design fully bidirectional and then just not use the Rx path? If that's the path of least resistance it's a pretty sad solution.

By comparison, the Altera SDI solution includes all of the customizations I listed above (Rx/Tx/bidirectional, which standards to support) and looks to be a much cleaner solution.
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Xilinx Employee
Xilinx Employee
13,642 Views
Registered: ‎07-31-2012
If only a receiver or only a transmitter is needed by the application, the input ports for the unused half of the core can be tied to ground and the output ports left unconnected. The synthesis tool will optimize the unused portion of the core out of the application.

This is kind of mentioned in the UG.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

View solution in original post

Explorer
Explorer
7,312 Views
Registered: ‎11-25-2014

Thanks for the response. Yeah, I was already heading down that path. Still disappointed by the cobbled-together nature of this IP. But at least it's free!

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Contributor
Contributor
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Registered: ‎12-10-2018

Hello!
I know this is a really old post, but I have encountered  a problem which is really related to this and I can't still solve it. I want to use the core for Tx only and I have made the connections as mentioned above. But in SD format, I have no video output. Any help is highly appreciated. I have explained the problem in more details here, but no one has answered yet!

https://forums.xilinx.com/t5/Xilinx-IP-Catalog/Error-in-SD-SDI-transmission-using-GTX/td-p/1076163

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