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mustafa60
Contributor
Contributor
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Registered: ‎07-17-2019

SMTPE296M

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Hi all,

I need to decode the information taken from a HD 720p camera which uses SMTPE296M embedded sync and progressive.  I write a code in verilog but it seems there is some problems at decoding EAV and SAV part. Can anyone show me where ı am wrong?

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07.08.2019 14:49:29
// Design Name:
// Module Name: bt1120torgb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

 

module bt1120torgb(
EndOfLine,
StartOfFrame,
iReady,
txout0_seven,
txout1_seven,
txout2_seven,
txout3_seven,
txclk_in,
oYCbCr,
data_valid,
reset
);

input iReady;
input [6:0] txout0_seven;
input [6:0] txout1_seven;
input [6:0] txout2_seven;
input [6:0] txout3_seven;
input txclk_in;
input reset;
output [23:0] oYCbCr;
output data_valid;
output StartOfFrame;
output EndOfLine;

reg[7:0] Y_eight;
reg[7:0] C_eight;

wire[7:0] Y;
wire[7:0] C;
reg[7:0] oY;
reg[7:0] oCb;
reg[7:0] oCr;

reg [23:0] oYCbCr;
reg [10:0] Hcount=11'd0;
reg [9:0] Vcount=10'd0;
reg Hsync,Vsync;
reg data_valid;
wire StartOfFrame;
reg EndOfLine;

 

assign StartOfFrame = (Hcount==11'd0 && Vcount==10'd26) ? 1:0;
always@(negedge txclk_in or negedge reset) begin // Y_eight and C_eight can be a assign block
if(!reset) begin
Y_eight<=0;
C_eight<=0;
end
else begin
Y_eight<= {{txout1_seven[0]},{txout0_seven}};
C_eight<= {{txout3_seven[0]},{txout2_seven}};
end
end

assign Y= Y_eight;
assign C= C_eight;

always@(negedge txclk_in) begin // horizontal synchronization pulse

if(Y==8'hB6)
Hsync <= 1;
else if (Y==8'h80)
Hsync<=0;
else if ( Y==8'h9D)
Hsync<=1;
else if (Y==8'hAB)
Hsync<=0;

end
//****************************************************************************
always@(negedge txclk_in) // HORİZONTAL AND VERTİCAL COUNTERS
begin

if(~Hsync) begin
Hcount<= Hcount + 11'd1;
if (Hcount==11'd1280) begin
EndOfLine<=1'b1;
Hcount<=1'b0;
Vcount<= Vcount+ 10'd1;
if (Vcount>=10'd26 && Vcount <=10'd745)
data_valid<=1'b1;
else
data_valid <=1'b0;

if(Vcount>10'd749)
begin
Vcount<=10'd0;
end
end
else
EndOfLine<=1'b0;
end
else
Hcount<=0;

end


// assign oYCbCr=iReady ? {oCr,oCb,oY}:24'd0;


always@(negedge txclk_in) begin

if(iReady)

oYCbCr <={oCr,oCb,oY};
else
oYCbCr <=24'd0;


end

//**************************************************** YC to YCbCr 4:2:2 converter

always@(negedge txclk_in or negedge reset) begin
if(!reset) begin
oY<=0;
oCb<=0;
oCr<=0;
end

else if (data_valid) begin

if(~Hcount[0]) begin
oY<=Y;
oCb<=C;
end

else begin
oY<=Y;
oCr<=C;
end
end
end

endmodule

 

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samk
Moderator
Moderator
685 Views
Registered: ‎10-04-2017

Hi @mustafa60,

 

I would suggest taking a look at XAPP1249 for SDI on 7-series devices.

This should answer your interface questions as well as what IP to use and how to find it.

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post

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9 Replies
wbyjerry
Adventurer
Adventurer
924 Views
Registered: ‎07-29-2013
I think it's need your detailed description to locate the problem.
mustafa60
Contributor
Contributor
893 Views
Registered: ‎07-17-2019

Firstly sorry i couldnt give a response for a while. The problem is that although i got the general idea about embedded sync.,  decoding the information is a little bit complicated for me in HDL. Information comes in such a way that txout0+-, txout1+-, txout2+-, txout3+- and txoutclk+- differential pairs form the camera as 7 bits.

I first need to decode this 7 bit to 8 bit. ([6:0]txout0+- is a first 7 bit Y and [6:6]txout1+- msb of Y info etc.) and extract the EAV and SAV information from the coming datas of the frame. In my code i first concenate datas as 8 bit in two different channel Y and C. Then i changed Hsyns pulse according to EAV and SAV infos according to specification sheet. I guess first problem is the way i did it in my code. Is it right?.

 

Also, data_valid flag informs me when the video data comes and i activate the output when the data_valid flag is asserted as 1. Does this way create me an empty space in between frames. Or should i take all information from the channel?.

 

Lastly, my EndOfLine and StartOfFrame flags are arramge like in the code. Is the logic behind it true?

 

 

I appreciate all answers and thank you a lot.

 

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samk
Moderator
Moderator
817 Views
Registered: ‎10-04-2017

Hi @mustafa60,

 

Writing an SDI receiver yourself will require deep knowledge of the SDI protocol. My suggestion would be to use one fo the IPs provided by Xilinx or possibly a partner.

 

See IP listings:

https://www.xilinx.com/content/xilinx/en/products/intellectual-property/ip-keyword-search.html#q=smpte&firstQueryCause=searchFromLink&firstQueryMeta={%22JSUIVersion%22:%222.4382.16%3B2.4382.16%22}

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
mustafa60
Contributor
Contributor
811 Views
Registered: ‎07-17-2019
I have a concern that this IP core supports SMPTE 296M which is not in the list ?
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mustafa60
Contributor
Contributor
804 Views
Registered: ‎07-17-2019
also my camera output is LVDS 30 pin . Does it matter?
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samk
Moderator
Moderator
793 Views
Registered: ‎10-04-2017

Hi @mustafa60,

 

SMPTE296M:

I believe SMPTE 296M is encompassed in the HD-SDI SMPTE 292 interface. (SMPTE296M defines the 720p resolution) Double-check the SMPTE documentationif you are not sure.

 

This is listed in one of our older docs XAPP1014.

2019-08-22 13_02_13-Xilinx Documentation Navigator 2018.3 -  https___www.xilinx.com_support_document.png

 

Interfaces:

The interfaces we use for our SDI solutions are defined in our PGs and what you use depends on which FPGA family you are targeting, but they use the GTs which are not 30pin LVDS interfaces.

XAPP592

XAPP1248

XAPP1290

XAPP1249

PG290 Appendix C.

 

What camera are you using that has a 30pin SMPTE interface? 

 

 

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
mustafa60
Contributor
Contributor
778 Views
Registered: ‎07-17-2019

TAMRON MP1110M-VC. The one ı am using. I would be very gratefull if you can check the spec. sheet. In the spec. sheet the camera gives output as 30 pin lvds but in TXOUT0,TXOUT1,TXOUT2 AND TXOUT3 outputs are in 7 bit. However, your cores input is 10 bit or 16. Should ı use zero paddle to give the input to the core or make Y and C component serialize ?. thank you very much for your efford.   

btw, I am using zc702 board.

 

Edit: As you said the data format is supported in SMPTE 292.  How to find this IP core preferibally free. ? 

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samk
Moderator
Moderator
686 Views
Registered: ‎10-04-2017

Hi @mustafa60,

 

I would suggest taking a look at XAPP1249 for SDI on 7-series devices.

This should answer your interface questions as well as what IP to use and how to find it.

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post

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aoifem
Moderator
Moderator
642 Views
Registered: ‎11-21-2018

Hi @mustafa60 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply).

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA


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