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Participant
Participant
1,183 Views
Registered: ‎07-05-2017

SP701 MIPI CSI Interface

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Hi

I'm having few queries regarding MIPI interface with FPGA.

1) In SP701 evaluation board, CSI and DSI interface is connected to two different banks. CSI being connected to 2.5V bank using a resistor network and DSI is connected to 1.8V bank. But in xapp894 it is given as below for CSI.

save.png

Here how HSUL_12_S_HR is compatible with 2.5V bank , please clarify.

2) If i'm implementing below circuitry for DSI (in Artix 7), can i connect MC2002 IOs to 1.8V bank ?

sa.png

3) If i'm implementing below circuitry for CSI (in Artix 7), can i connect MC2001 IOs to 1.8V bank ? Is 2.5V bank voltage mandatory for CSI interface ?

sa1.png

Please reply.

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Xilinx Employee
Xilinx Employee
1,099 Views
Registered: ‎03-30-2016

Hello @bivin 

>3) Please confirm with Meticom ICs (MC20901,MC20902) i have to use always 2.5V banks in Artix 7 .

You can go to Meticom URL and download their datasheet. You need to use 2.5V. (Requirement from Meticom)
http://www.meticom.com/resources/Datasheets/MC20002-V1_08.pdf
http://www.meticom.com/resources/Datasheets/MC20001-V1_09.pdf

>2) Is there any validation tool/checklist for the same ?

You can use Vivado to check whether your pin assignment is correct or not.
Please create a test design, plan your pin-assignment, and implement your test design.
Vivado will check whether your pin-assignment is good to go.

>1) Is there any specific IO to which i need to connect HS_P/N as well as LP_P/N ?

Could you please check PG202 Appendix C and UG471.
EC_7series_pin_rules.png

Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
1,139 Views
Registered: ‎03-30-2016

Hello @bivin 

2) If i'm implementing below circuitry for DSI (in Artix 7), can i connect MC2002 IOs to 1.8V bank ?

No.

3) If i'm implementing below circuitry for CSI (in Artix 7), can i connect MC2001 IOs to 1.8V bank ? Is 2.5V bank voltage mandatory for CSI interface ?

No, it is not a mandatory but I believe MC2001/MC2002 only support 2.5V.
-- The requirement/limitation is on Meticom devices.


1) In SP701 evaluation board, CSI and DSI interface is connected to two different banks.
CSI being connected to 2.5V bank using a resistor network and DSI is connected to 1.8V bank. But in xapp894 it is given as below for CSI.


It should be possible I think. (See table below). Could you please check UG471 ?


Thanks & regards
Leo

XF_UG471_clarification.png
Participant
Participant
1,131 Views
Registered: ‎07-05-2017

Hi @karnanl 

Thanks for the reply. I'm having few queries.

1) Is there any specific IO to which i need to connect HS_P/N as well as LP_P/N ?

2) Is there any validation tool/checklist for the same ?

3) Please confirm with Meticom ICs (MC20901,MC20902) i have to use always 2.5V banks in Artix 7 .

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Reply
Xilinx Employee
Xilinx Employee
1,100 Views
Registered: ‎03-30-2016

Hello @bivin 

>3) Please confirm with Meticom ICs (MC20901,MC20902) i have to use always 2.5V banks in Artix 7 .

You can go to Meticom URL and download their datasheet. You need to use 2.5V. (Requirement from Meticom)
http://www.meticom.com/resources/Datasheets/MC20002-V1_08.pdf
http://www.meticom.com/resources/Datasheets/MC20001-V1_09.pdf

>2) Is there any validation tool/checklist for the same ?

You can use Vivado to check whether your pin assignment is correct or not.
Please create a test design, plan your pin-assignment, and implement your test design.
Vivado will check whether your pin-assignment is good to go.

>1) Is there any specific IO to which i need to connect HS_P/N as well as LP_P/N ?

Could you please check PG202 Appendix C and UG471.
EC_7series_pin_rules.png

Thanks & regards
Leo

View solution in original post