02-15-2021 02:54 AM
I have been trying to implement the MIPI CSI-2 Rx Subsystem with a single DMA connected with PS. I will take the image to the PS by using the DMA, for this purpose I am using PYNQ. I have to send the command from PS through IIC as far as I can understand.
It will be very helpful if someone can share a simple block diagram/script or the modified constraints file from the MIPI Rx subsystem example which is for ZCU102 board.
Any help would be really appreciated.
02-15-2021 04:02 AM
Pardon me but there is no script available to generate MIPI CSI-2 Example Design for ZCU104 board.
If you need to migrate MIPI CSI-2 Example Design (from ZCU102 board) to ZCU104 board, you need to change the design manually.
02-15-2021 05:17 AM
Yes, that's what I am doing, but the problem is without the modified constraints file, It becomes very difficult. Stil I have tried the last 2 weeks and in the end, I came up with a problem for which there are many ones suffering to implement MIPI in ZCU104. That's related to the bg0_pin0_nc pin. I (along with many one) don't know where to connect it. Someone solved this problem using D16 for using bank 67 for their data lines. But in my case, I am using bank 68 which is connected to my external deserializer. Now I am stuck with many errors. Please help me with some advice.
02-16-2021 01:58 AM
>I came up with a problem for which there are many ones suffering to implement MIPI in ZCU104.
>That's related to the bg0_pin0_nc pin. I (along with many one) don't know where to connect it.
bg*_pin*_nc pins may appears if you select pins across multiple bytegroups for your MIPI D-PHY IP.
These pins should not be generated if you assigned all pins in a single bytegroups.
BTW, we have explanations on bg pins in PG202. See also explanation below.
02-16-2021 02:44 AM
Thank you @karnanl for the reference.
I already have read the above reference and also MIPI dphy. It automatically shows up when the example design for zcu102 updated for zcu104. I really don't understand why this comes in Zcu104 and not in zcu102.
And, not connecting this shows different errors and also connecting this to external pin drives to other errors. Some of them (Not all) are following.
DRC PDRC-187. I found someone facing almost a similar problem in this Link and I am also using a deserializer like him.
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 68. For example, the following two ports in this bank have conflicting VCCOs: IIC_sensor_scl_io (LVCMOS12, requiring VCCO=1.200) and IIC_sensor_sda_io (LVCMOS18, requiring VCCO=1.800).
I know this error not related to that pin but it comes somehow because of that. Even if I set it up it's iostandard to lvcmos33 in the constraints file. It goes away if I connect that nc pin to an external pin.
If I don't connect this, sometime this following error comes
[Place 30-687] Expected cell design_1_i/mipi_csi2_rx_subsystem_0/U0/phy/inst/inst/bd_bf15_phy_0_rx_support_i/slave_rx.bd_bf15_phy_0_rx_hssio_i/inst/top_inst/bs_top_inst/u_rx_bs/RX_BS.rx_bitslice_if_bs be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.
02-16-2021 03:30 AM
Please connect those bg_pins to top layer module.
>I really don't understand why this comes in Zcu104 and not in zcu102.
This because your MIPI IP's pin assignment is different from pin assignment on ZCU102 board case.
>[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 68. For example, the following two ports in this bank have conflicting VCCOs: IIC_sensor_scl_io (LVCMOS12, requiring VCCO=1.200) and IIC_sensor_sda_io (LVCMOS18, requiring VCCO=1.800).
This is different issue. MIPI_DPHY_DCI IO standard requires VCCO=1.2V.
But , it seems you mixed up some IO standards with different VCCO setting on the same bank68.