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Explorer
Explorer
1,617 Views
Registered: ‎08-31-2016

Serial transceiver txoutclk is not being generated

Hi,

 

I've designed the TX only SDI design for ZCU102 from ZCU106 12G-SDI pass through example design. 

Modified the example design as required for TX only design. 

 

The serial transceiver reference clock is given from the FMC card, which has a 148.5 Mhz  clk oscillator (default clk out).

 

I am not able to get the txoutclk from the GT core.  I've double verified my reference clk and transceiver constraints on the .xdc file.

 

Regards,

Vinay

Vinay Shenoy
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Moderator
Moderator
1,564 Views
Registered: ‎11-09-2015

Hi @vinay_shenoy,

 

How are you checking the TXOUTCLOCK?

Could you make sure the GT is not held in reset?

Did you check the configuration (MGTREFCLK selection?).

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Explorer
Explorer
1,538 Views
Registered: ‎08-31-2016

Hi,

I suspect a problem with the SDI GT in the design. Adding the GT signals to ILA for debug. Will update you

Regards,
Vinay
Vinay Shenoy
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@vinay_shenoy

 

From the last email from your SR, you were able to get TX and RX RESETDONE. Is txoutclk still not being generated?

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Moderator
Moderator
1,471 Views
Registered: ‎11-09-2015

Hi @vinay_shenoy

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" buton below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
1,463 Views
Registered: ‎08-31-2016

Hi @florentw @xud

 

I am away from this debugging for sometime now. Surely I'll update the findings and observations.

 

Regards,

Vinay

Vinay Shenoy
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Moderator
Moderator
1,339 Views
Registered: ‎11-09-2015

Hi @vinay_shenoy,

 

Any update on this?

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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