cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
5,090 Views
Registered: ‎08-21-2013

Setting the DDS Phase Increment from Zynq ARM CPU

Hi,

 

I am trying to use the DDS Compiler IP Core (v6.0) to generate a sine wave, where I can set the frequency from within the ARM CPU. I am using a single channel sine output. 

 

As far as I understand, to do this I need to send a single word packet to the configuration stream input of the dds core (containing the new phase increment value). What is the best way of writing from the CPU to this configuration stream? I am trying to use the AXI-Stream FIFO (v4.0) Core to convert from memory mapped data to stream data, but the documentation says that a minimum of 4 words can be transferred per packet. Is there some other way to transmit a single word packet from the cpu to an axi-stream interface, or would I have to create my own peripheral?

 

Thanks,

 

Ryan 

 

0 Kudos
1 Reply
Highlighted
Teacher
Teacher
5,065 Views
Registered: ‎03-31-2012

Re: Setting the DDS Phase Increment from Zynq ARM CPU

I think the easiest solution would be to make an AXI GPIO and drive the tdata and tvalid signal with the GPIO signals. Then connect the AXI port to one of the general purpose AXI busses on the Zynq PL side.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos