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C-Ramesh
Visitor
Visitor
346 Views
Registered: ‎02-01-2021

Simulating Block Design which involves AXI4 Processor interface

Sir

I want to view the Native video ( RGB24 ,HS,VS) in hdmi using ZCU106 board.

I want to simulate the video pattern generator output and view in Model sim

 

CRamesh_0-1626936152928.png

 

Work carried out

1) Made block design - simple and validated 

2) created wrapper and tet bench file

3) simulated

Problem

No data output coming from Video pattern gen IP block.

CRamesh_1-1626936368687.png

 

 

Pls suggest

 

 

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11 Replies
dpaul24
Scholar
Scholar
339 Views
Registered: ‎08-07-2014

@C-Ramesh ,

How do you expect your design to design when do not connect the most basic thing such as the reset to the vid-out block?

The aresetn is unconnected.

Also do you see those two yellow lines in the waveform? It indicates that they are not driven.

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francocapraro12
Adventurer
Adventurer
304 Views
Registered: ‎09-27-2018

Hi @C-Ramesh ,

Can you provide the testbench file to see it. 
Also check if your testbench file is set as Top in the Simulation part. You can check a tutorial in the forum:
https://forums.xilinx.com/t5/Video-and-Audio/Video-Beginner-Series-4-Simulation-with-the-Xilinx-TPG-IP/td-p/855134

Best,
FC

C-Ramesh
Visitor
Visitor
287 Views
Registered: ‎02-01-2021

Dear Paul

Thanks.

I have tied with reset and clock. Output of video out ( AXI4 -Stream to video out) is keep as open.

Now i am not using the AXI4 control interface.

I have wrote clock logic in top design wrapper .

I want to simulate this Block design of video test pattern

There is no improvement. Clk net and Reset to Logic is showing " U state"

Pls help me

Regards

Ramesh

 

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francocapraro12
Adventurer
Adventurer
276 Views
Registered: ‎09-27-2018

Hi @C-Ramesh ,

I recommend you to see the tutorial that i sent you.
In your design, you can reduce the complexity, deleting the cloking wizard and system reset.

After that, you can implement a "clock source" in you testbench code in this way ( This contain just a part of the testbench, please finish it):


module tb_full(

    );

reg  s_axi_aclk_0=0;
reg reset=0;
...... // MORE reg that you need


block_design design_1_i
       (..........);


  integer i;

 initial 
        begin
            for (i=0   ;i< 10; i=i+1) 
            begin
             //THIS WILL GENERATE A 100MHZ CLOCK
            #5 s_axi_aclk_0= ~s_axi_aclk_0;
            end
        reset=1;
            for (i=0   ;i< 2800; i=i+1) 
            begin
            #5 s_axi_aclk_0= ~s_axi_aclk_0;
            end
  end
        
        
endmodule

Best,

FC

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dpaul24
Scholar
Scholar
273 Views
Registered: ‎08-07-2014

@C-Ramesh ,

I want to simulate this Block design of video test pattern

There is no improvement. Clk net and Reset to Logic is showing " U state"

In that case I would say that those signals are not being properly driven from the testbench.

Post your testbench (within code tags or as an attachment, do not just paste it here).

Note that if you do not tag me, it is very much possible that I will not read this thread in the future.

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watari
Professor
Professor
270 Views
Registered: ‎06-16-2013

Hi @C-Ramesh 

 

Why don't you use Simulation IPs ?

I'm sure that you can build simulation environment by GUI.

 

- Simulation Clock generator

- Simulation Reset Generator

- AXI Verification IP

- AXI4-Stream Verification IP

- AXI Traffic Generator

 

Best regards,

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C-Ramesh
Visitor
Visitor
200 Views
Registered: ‎02-01-2021

Dear Experts

Two things are not Clear to me.

Reset , and clock managed by simulation block. Blog is not  much explaining the below details.

1) m_axis_video_ready 

2) How to program the video test pattern register using VIP block?

I am going through the VIP AXI  document. Pls through some light on this area

Your suggestion helps  me to make the things

Regards

Ramesh

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watari
Professor
Professor
156 Views
Registered: ‎06-16-2013

Hi @C-Ramesh 

 

Did you refer PG267 ?

 

https://www.xilinx.com/support/documentation/ip_documentation/axi_vip/v1_1/pg267-axi-vip.pdf

 

Also, I suggest you to refer xilinx-vip-api-2019.1.zip .

 

https://www.xilinx.com/products/intellectual-property/axi-vip.html#documentation

 

Would you try them ?

 

Hope this helps.

 

Best regards,

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dpaul24
Scholar
Scholar
130 Views
Registered: ‎08-07-2014

@C-Ramesh ,

There is no improvement. Clk net and Reset to Logic is showing " U state"

Pls help me

From the sim waveform it seems the main problem is how you are driving the clock and rest signals. You think you are driving those signals correctly, and if it is so, they would show up in the waveform.

I asked you to post the testbench but you didn't. If you are doing everything correctly, why are you shying away?

If you want help from me, post your testbench  (and do not forget to tag me) where the DUT is instantiated and its ports are driven.

 

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C-Ramesh
Visitor
Visitor
57 Views
Registered: ‎02-01-2021

Sir

I have gone though AXI Verification IP v1.1LogiCORE IP & downloaded the xilinx-vip-api-2019.1.zip

As per PG 267, Document is explaining the test simulation with respect to Table 6-1:Simulation Sets for AXI VIP. - It related with system Verilog. I could not able to find the system Verilog files , Second There is no sample Design w.r.t to Table 6.1.

I am sending simple GPIO design with VIP.

Will you provide some sample system Verilog file to simulate the AXIO GPIO.?

Pls suggest. ( simple gpio - vip attached , validated)

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C-Ramesh
Visitor
Visitor
42 Views
Registered: ‎02-01-2021

Sir

As per pg267-axi-vip.pdf , opened the example project suggested

While simulation it is giving following error

attached with this mail ( elabrate.log)

Pls suggest

 

 

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