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Visitor
Visitor
4,173 Views
Registered: ‎07-19-2008

Some question about System Generator

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Hi everyone,

I'm new to System Generator. I just used Xilinx ISE to design FPGA in VHDL before with Spartan 3E starter kit. But now I found out System Generator with more useful math block.

But I really have many question that keep spining in my mind although I have read all the pdf starter guide and lab module:

 

1. Is it ok to use sin, cos and gaussian noise of xilinx system generator block with Spartan 3E starter kit?

2. I could find exp function in Xilinx block, so does that mean exp function does not appear in Xilinx block?

3. Does it have any way to download to FPGA directly? I think I have to export model of System Generator to VHDL code, and then make a component in ISE.

 

I really appreciate any helps. 

_______________________________________________________________________
there 10 types of people in the world: those who knows binary and those who don't
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Contributor
Contributor
4,536 Views
Registered: ‎04-03-2009

Hi!

 

I'm not an expert so somebody might correct me.

1. sin and cos can be computed using CORDIC or with the DDS Compiler. Latter is basically a look up table, and depending on the resolution you require it will occupy some BRAM-s and minimal logic in your FPGA. CORDIC computes the values, using no BRAMs but more logic (adders and shifters). You should use resource estimator to see how much resources a certain configuration will eat up. Depending on precision requirements and device size it might fit into a Spartan 3E.

The White Gaussian Noise Genearator seems quite complicated. As i see it uses at least 4 multipliers and lots of logic. Check with resource estimator if it will fit.

2.With the CORDIC 4.0 block from the Xilinx Blockset you can compute sinh and cosh (e^x = sinh x+ cosh x).

3.Double click your System Generator block and set Compilation to Bitstream then System Generator should produce a downloadable .bit file for the selected device. You can download the file with Impact.

 

Message Edited by bagojfalvibagoj on 12-06-2009 08:49 PM
Message Edited by bagojfalvibagoj on 12-06-2009 08:50 PM

View solution in original post

3 Replies
Contributor
Contributor
4,537 Views
Registered: ‎04-03-2009

Hi!

 

I'm not an expert so somebody might correct me.

1. sin and cos can be computed using CORDIC or with the DDS Compiler. Latter is basically a look up table, and depending on the resolution you require it will occupy some BRAM-s and minimal logic in your FPGA. CORDIC computes the values, using no BRAMs but more logic (adders and shifters). You should use resource estimator to see how much resources a certain configuration will eat up. Depending on precision requirements and device size it might fit into a Spartan 3E.

The White Gaussian Noise Genearator seems quite complicated. As i see it uses at least 4 multipliers and lots of logic. Check with resource estimator if it will fit.

2.With the CORDIC 4.0 block from the Xilinx Blockset you can compute sinh and cosh (e^x = sinh x+ cosh x).

3.Double click your System Generator block and set Compilation to Bitstream then System Generator should produce a downloadable .bit file for the selected device. You can download the file with Impact.

 

Message Edited by bagojfalvibagoj on 12-06-2009 08:49 PM
Message Edited by bagojfalvibagoj on 12-06-2009 08:50 PM

View solution in original post

Visitor
Visitor
4,115 Views
Registered: ‎07-19-2008

Hi bagojfalvibagoj,

 

I really appreciate your help. I forgot sinh and cosh function. My problems have solved!

 

Best regards,

 

Phong Duong 

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there 10 types of people in the world: those who knows binary and those who don't
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Xilinx Employee
Xilinx Employee
4,112 Views
Registered: ‎11-28-2007

Regarding your question 3: you can also use the hardware cosimulation in sysgen to download your design to FPGA and test it in HW. The snapshot below shows the compilation target for HW cosimulation.

 

 

Cheers,
Jim
hwcosim.gif
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