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Voyager
Voyager
3,101 Views
Registered: ‎05-09-2008

SysGen 13.2 and HDL generation ...

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Hi,

I have problem (creed) with  compilation  of  model with new device using System
Edition 13.2 of xilinx software. I'll explain:

I have "Fractional rate upsampler"  that  I found on xilinx application xapp936,
that it works very fine with little change of num_phases to 1024 and data input
to signed 16 bit and fractional part of 15.

I have board with spartan 3A DSP 3400 -4 speed grade on CS484 case. With help of
Matlab I have generate HDL  Netlist from xapp936  model  with  default
scheme  clocking  of  13.5 nS.  Matlab  with System Generator 13.2 make HDL code
without any problem. After generation I open ISE project and start "Place and
Route process". The software working well and this is a result :

 

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.088ns (Maximum Frequency: 123.640MHz)
   Minimum input arrival time before clock: 7.589ns
   Maximum output required time after clock: 5.531ns
   Maximum combinational path delay: 1.631ns

...

Starting Router


Phase  1  : 9420 unrouted;      REAL time: 27 secs

Phase  2  : 3358 unrouted;      REAL time: 28 secs

Phase  3  : 689 unrouted;      REAL time: 30 secs

Phase  4  : 689 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 31 secs

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 33 secs

Updating file: frational_debug_cw.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 34 secs

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 34 secs

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 34 secs

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |  BUFGMUX_X1Y0| No   |  688 |  0.361     |  1.857      |
+---------------------+--------------+------+------+------------+-------------+

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing  
                                            |             |    Slack   | Achievable | Errors |    Score  
----------------------------------------------------------------------------------------------------------
  TS_clk_c3c4f78d = PERIOD TIMEGRP "clk_c3c | SETUP       |     1.836ns|    11.664ns|       0|           0
  4f78d" 13.5 ns HIGH 50%                   | HOLD        |     0.567ns|            |       0|           0
----------------------------------------------------------------------------------------------------------

 

 Few days ago I have bought a Avnet Spartan 6 LX150T Development board. I did the
same thing earlier, generating HDL, but for the new device XC6SLX150T-3FGG676 I
do not obtain the same performance for Setup & Hold. This is a a result :

 

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 2.428ns (Maximum Frequency: 411.839MHz)
   Minimum input arrival time before clock: 3.797ns
   Maximum output required time after clock: 3.597ns
   Maximum combinational path delay: 1.222ns

...

Starting Router


Phase  1  : 7748 unrouted;      REAL time: 10 secs

Phase  2  : 3266 unrouted;      REAL time: 12 secs

Phase  3  : 537 unrouted;      REAL time: 22 secs

Phase  4  : 537 unrouted; (Setup:0, Hold:118998, Component Switching Limit:0)     REAL time: 26 secs

Updating file: frational_debug_cw.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:0, Hold:116982, Component Switching Limit:0)     REAL time: 30 secs

Phase  6  : 0 unrouted; (Setup:0, Hold:116982, Component Switching Limit:0)     REAL time: 30 secs

Phase  7  : 0 unrouted; (Setup:0, Hold:116982, Component Switching Limit:0)     REAL time: 30 secs

Phase  8  : 0 unrouted; (Setup:0, Hold:116982, Component Switching Limit:0)     REAL time: 30 secs
WARNING:Route:466 - Unusually high hold time violation detected among 28 connections. The top 20 such instances are printed below. The
   router will continue and try to fix it
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/delay_q_net(3):DQ ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram1/comp5.core_instance5/U0/xst_blk_mem_generato
r/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA7 -3057
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/delay_q_net(3):BQ ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram1/comp5.core_instance5/U0/xst_blk_mem_generato
r/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA5 -3057
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/delay_q_net(3):AQ ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram1/comp5.core_instance5/U0/xst_blk_mem_generato
r/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA4 -3057
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/delay_q_net(3):BMUX ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram1/comp5.core_instance5/U0/xst_blk_mem_generato
r/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA9 -3011
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/delay_q_net(3):CQ ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram1/comp5.core_instance5/U0/xst_blk_mem_generato
r/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA6 -2901
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/delay_q_net(3):AMUX ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram1/comp5.core_instance5/U0/xst_blk_mem_generato
r/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA8 -2860
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/delay_q_net(3):DMUX ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram1/comp5.core_instance5/U0/xst_blk_mem_generato
r/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA11 -2837
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/delay_q_net(9):CQ ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram1/comp5.core_instance5/U0/xst_blk_mem_generato
r/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA12 -2829
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/delay_q_net(9):DQ ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram1/comp5.core_instance5/U0/xst_blk_mem_generato
r/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA13 -2812
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/delay_q_net(3):CMUX ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram1/comp5.core_instance5/U0/xst_blk_mem_generato
r/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA10 -2796
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/delay_q_net(9):BQ ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram/comp4.core_instance4/U0/xst_blk_mem_generator
/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA13 -2506
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/delay3_q_net_x1(3):BQ ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram/comp4.core_instance4/U0/xst_blk_mem_generator
/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA5 -2483
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/delay3_q_net_x1(3):AQ ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram/comp4.core_instance4/U0/xst_blk_mem_generator
/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA4 -2483
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/delay3_q_net_x1(3):DQ ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram/comp4.core_instance4/U0/xst_blk_mem_generator
/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA7 -2482
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/delay_q_net(9):AQ ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram/comp4.core_instance4/U0/xst_blk_mem_generator
/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA12 -2458
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/delay3_q_net_x1(3):BMUX ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram/comp4.core_instance4/U0/xst_blk_mem_generator
/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA9 -2437
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/delay3_q_net_x1(3):CQ ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram/comp4.core_instance4/U0/xst_blk_mem_generator
/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA6 -2327
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/delay3_q_net_x1(3):AMUX ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram/comp4.core_instance4/U0/xst_blk_mem_generator
/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA8 -2286
    frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/delay3_q_net_x1(3):DMUX ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps3_294fdeebb1/single_port_ram/comp4.core_instance4/U0/xst_blk_mem_generator
/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA11 -2263
    frational_debug_x0/resampler_ec073b13fa/addr_gen_26443a7afc/delay_q_net(29):BMUX ->
frational_debug_x0/resampler_ec073b13fa/filter_bb047cbff6/two_taps4_dfd6c7ed76/single_port_ram/comp6.core_instance6/U0/xst_blk_mem_generator
/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram:ADDRA9 -2229


Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 31 secs

Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 31 secs

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|       clk_IBUF_BUFG | BUFGMUX_X3Y13| No   |  266 |  0.151     |  1.414      |
+---------------------+--------------+------+------+------------+-------------+
|            clk_IBUF |         Local|      |    9 |  3.529     |  6.355      |
+---------------------+--------------+------+------+------------+-------------+

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing  
                                            |             |    Slack   | Achievable | Errors |    Score  
----------------------------------------------------------------------------------------------------------
  TS_clk_c3c4f78d = PERIOD TIMEGRP "clk_c3c | SETUP       |     2.884ns|    10.616ns|       0|           0
  4f78d" 13.5 ns HIGH 50%                   | HOLD        |     0.053ns|            |       0|           0
----------------------------------------------------------------------------------------------------------

 

Why I obtain a performance degradation on setup and hold time ?

 

With other version of model, precision, number of taps and others, the router will continue and can not fix it. Same model on spartna 3A DSP work well without any problem.

 

The clock is no very expensive and the device is the fastest of its family.

Where can I find the problem ?

Thanks very much.

secureasm

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Voyager
Voyager
3,332 Views
Registered: ‎05-09-2008

Hi,

 

I have found a solution, you must enable "read_core" options in the "Synthesis Options".

 

Synthesis Options.png

 

Now working, no problem of timing.

 

secureasm.

 

 

View solution in original post

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Voyager
Voyager
3,333 Views
Registered: ‎05-09-2008

Hi,

 

I have found a solution, you must enable "read_core" options in the "Synthesis Options".

 

Synthesis Options.png

 

Now working, no problem of timing.

 

secureasm.

 

 

View solution in original post

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