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grando
Observer
Observer
3,725 Views
Registered: ‎09-15-2009

SysGen - issues with HW-cosimulation of vhdl code in blackbox

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Hi everybody,

 

I imported a VHDL code (quite simple) to simulink using a blackbox, and now I want to test it using hw cosimulation.

The code works with my testbench, it works in the simulink simulation, it works with the testbench generated by system generator.

Then I added the hwcosim block to the design and conect it to the scope block, in order to run hw-cosimulation.

But when I compare the output of the black box with the corresponding hwcosim block, they are completely different.

I checked the requirements on HDL for blackboxes, it seems to be everything correct.

 

Does anyone have an idea what could be the problem?

 

I'm using Matlab R2010a and ISE Design Suite 12.3. The board is a XUPV5-LX110T.

 

Any help will be very appreciated.

 

Thanks in advance,

Carmela

 

 

 

 

 

 

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eilert
Teacher
Teacher
4,061 Views
Registered: ‎08-14-2007

Hi Carmela,

you probably just observed why it is very important to simulate the netlist created by some HDL code.

Using HW-Cosim for that purpose can be faster than doing a post-par simulation with a simulation tool.

 

With out knowing your code and tool reports I can only guess, but there's a good chance that your code is written in a way that produces different results for simulation and synthesis.

This can have several causes.

- Wrong sensitivity lists

- using unsupported statements for synthesis (e.g. after)

- a tool bug (unlikely but possible)

 

You should take a look at the synthesis report (.syr file) and check for infos and warnings that appear.

Most probably you find some hint there.

 

Have a nice synthesis

  Eilert

 

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2 Replies
eilert
Teacher
Teacher
4,062 Views
Registered: ‎08-14-2007

Hi Carmela,

you probably just observed why it is very important to simulate the netlist created by some HDL code.

Using HW-Cosim for that purpose can be faster than doing a post-par simulation with a simulation tool.

 

With out knowing your code and tool reports I can only guess, but there's a good chance that your code is written in a way that produces different results for simulation and synthesis.

This can have several causes.

- Wrong sensitivity lists

- using unsupported statements for synthesis (e.g. after)

- a tool bug (unlikely but possible)

 

You should take a look at the synthesis report (.syr file) and check for infos and warnings that appear.

Most probably you find some hint there.

 

Have a nice synthesis

  Eilert

 

View solution in original post

grando
Observer
Observer
3,722 Views
Registered: ‎09-15-2009

Hi,

 

it's embarassing....

I didn't realize before that one input of the hwcosim block was in a diferent position than everywhere else, and thus connected the signals in the same order as with the black box. First noticed that after I built the model from the beginning.

 

 

Anyway, thank you very much for your time and attention!

 

Regards,
Carmela

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