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Registered: ‎02-18-2008

System Generator and GTP Transceivers

I am trying to use System Generator in Simulink to implement my design. I need to put the generated signals onto the GTP Transmitter. I am trying to use the Xilinx Gateway Block to specify the pins for the GTP transceivers and then using system generator to generate a bitstream. I get the following error message:
ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB
    BUF symbol "gateway_out2_OBUF" (Output Signal = gateway_out2)
    PAD symbol "gateway_out2" (Pad Signal = gateway_out2)
   Each of the following constraints specifies an illegal physical site for a
   component of type IOB:
    Symbol "gateway_out2" (LOC=L2 [Physical Site Type = OPAD])
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. Please double check that the types of
   logic elements and all of their relevant properties and configuration options
   are compatible with the physical site type of the constraint.
   Please correct the constraints accordingly.
What am I doing wrong?
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1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2007

Hi Arwa,

So are you wanting to have your entire design in Sysgen?

This is typically done by generating the hdl files for your sysgen design then putting this into a top level design in ISE with the GTP instantiations. The GTP's are not available as blocks in Sysgen.

You can however define LOC's in the gateway in/out blocks.

RJ Duran
Customer Application Engineer
Technical Support:
Xilinx User Community:
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