TPG+VDMA+HDMI ON ZC706 Board

[jia149751]

vivado2014.4

    I download the prj from https://github.com/analogdevicesinc/hdl

    set for zc706 board, now HDMI is OK on monitor, but I add TPG and set VDMA write enable,

    but HDMI is not normal show tartan bars pattern in monitor, monitor show is not like my image, actually show like RGB stripe,

    can you help me where is not correct? 

    Thank you very much!!!

[jia149751]

monito show like this,who can help me?

[florentw]

HI @jia149751,

How did you programmed the VDMA? It looks like a configuration issue

[jia149751]

VDMA SET:

 /***************************************************************/
 //add VDMA ctrl by jxd zzcx 20190110

    Xil_Out32(VDMA_BASEADDR + 0x30, 0x4); //reset   S2MM VDMA Control Register
    Xil_Out32(VDMA_BASEADDR + 0x30, 0x8); //genlock
    Xil_Out32(VDMA_BASEADDR + 0xAC,   0x08000000);//S2MM Start Addresses
    Xil_Out32(VDMA_BASEADDR + 0xAC+4, 0x0A000000);
    Xil_Out32(VDMA_BASEADDR + 0xAC+8, 0x0D000000);
    Xil_Out32(VDMA_BASEADDR + 0xA4, (640*4));//S2MM Horizontal Size
    Xil_Out32(VDMA_BASEADDR + 0xA8, (640*4));//S2MM Frame Delay and Stride
    Xil_Out32(VDMA_BASEADDR + 0x30, 0x3);//S2MM VDMA Control Register
    Xil_Out32(VDMA_BASEADDR + 0xA0, 480);//S2MM Vertical Size  start an S2M
    Xil_DCacheFlush();

 /***************************************************************/

 Xil_Out32((VDMA_BASEADDR + AXI_VDMA_REG_DMA_CTRL),
     0x00000003); // enable circular mode
 /***************************************************************/
 //modify VDMA frame address by jxd zzcx 20190110

    Xil_Out32((VDMA_BASEADDR + AXI_VDMA_REG_START_1),
            0x08000000); // start address
    Xil_Out32((VDMA_BASEADDR + AXI_VDMA_REG_START_2),
            0x0A000000); // start address
    Xil_Out32((VDMA_BASEADDR + AXI_VDMA_REG_START_3),
            0x0D000000); // start address
 /***************************************************************/

 Xil_Out32((VDMA_BASEADDR + AXI_VDMA_REG_FRMDLY_STRIDE),
     (horizontalActiveTime*4)); // h offset
 Xil_Out32((VDMA_BASEADDR + AXI_VDMA_REG_H_SIZE),
     (horizontalActiveTime*4)); // h size
 Xil_Out32((VDMA_BASEADDR + AXI_VDMA_REG_V_SIZE),
     verticalActiveTime); // v size

[watari]

Hi @jia149751

Could you shre the followings ?

- Pitcure to output color bar, gray scale and RGB ramp image (gradation)

- Timing report file

Best regards,

[jia149751]

sorry,I don't understand very well about your means.

your means:

TPG output set: color bars and share the timing report file, Am I right?

[florentw]

Hi @jia149751,

I do not unserstand why you program your HSIZE as 640*4? You are using 8 bit per component and 3 component per pixel. So you should have 3 byte per pixel, thus your HSIZE might be 640*3 unless I am missing something?

[florentw]

HI @jia149751,

Do you have any updates on this?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,

[jia149751]

ADI HDMI_TX use VDAMdata[55:32] and [23:0],so I change TPG output data [23:0] to VDMAdata={8'h0,TPG[23:0],8'h0,TPG[23:0]},

so set pixel*4, now 640x480,monitor display is OK, but 1920x1080,monitor display likes below:

from 640x480 to 1600x900 are OK, why 1920x1080 is wrong, can anyone tell me somthing,thanks!

  

[watari]

Hi @jia149751

Would you tell me the following questions ?

1) What clock frequency do you use in a) 640x480, b) 1600x900 and c) 1920x1080 ?

2) What HSIZE do you program in a) 640x480, b) 1600x900 and c) 1920x1080 ?

Best regards,

[jia149751]

1) What clock frequency do you use in a) 640x480, b) 1600x900 and c) 1920x1080 ?

TPG:100MHZ

VDMA:100MHZ

HDMI: a) 640x480 :25MHZ   b) 1600x900:108MHZ   c) 1920x1080: 148.5MHZ

2) What HSIZE do you program in a) 640x480, b) 1600x900 and c) 1920x1080 ?

(horizontalActiveTime*4);

used the HDMI core expects 2 pixel at once, how TPG generates 2 pixels as well ?

[watari · Accepted solution]

Hi @jia149751

I recommend to change AXI4Stream clock frequency from 100MHz to at least over 133.333MHz. (Need to change some parameter, too) But I recommend to change ASI4Stream clock to 150MHz.

It's AXI4Stream band width issue, when the target resolution is 1920x1080.

Would you consider and change it ?

Best regards,

[florentw]

Hi @jia149751 ,

Do you have any updates on this? Did you make any progress? Is your issue solved?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,

[jia149751]

TPG:148.5MHZ

VDMA:148.5MHZ

Problem is solved, Thanks every one for answer to me!