cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
gayanca
Visitor
Visitor
2,665 Views
Registered: ‎07-20-2009

Taking multiple clock outputs

Hi

 

Are there are any means to get mutiple clock frequencies from FPGA, which runs on system clock?

 

Are there any blocks in XSG to achieve above directly?

 

Thanks in advance.  

0 Kudos
1 Reply
jeffreyh
Xilinx Employee
Xilinx Employee
2,451 Views
Registered: ‎08-07-2007

SysGen can support multiple sample rates which are all derived from one system clock.  It can also create designs which require multiple clock inputs running at any arbitrary rates relative to one another.

 

See the upsample and downsample blocks as well as the multiple subysystem generator token for details on each option.

0 Kudos