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thomasmurphyge
Observer
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Registered: ‎09-20-2018

Test Pattern Generator (TPG) Behavior Change 2018.2 -> 2019.1

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I developed a naive video subsystem for MIPI DSI output testing using a Video Frame Buffer Read (v_frmbuf_rd) cascaded into a Video Test Pattern Generator (v_tpg) in Vivado 2018.2 which I have since migrated to 2019.1. The IPs are only reset at the system and clock initial startup assertion and then run freely after. With the 2018.2 bitfile, I can enable TPG pass-through, start frame buffer generation, and then toggle pass-through mode with successful (if not correctly frame-synchronized on the frame buffer read stream) video from both sources. With the 2019.1 bitfile, turning off pass-through mode results in a fragment of the test pattern frame being visibly generated, then the display goes dark and toggling pass-through mode never results in video reaching the display from either source. Has there been a change between these versions that requires the TPG to be reset before reconfiguring its operation as a pass-through for AXI-S video?

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samk
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Registered: ‎10-04-2017

Hi @thomasmurphyge,

 

Here is the section from PG103, December 5, 2018. It is here to show that processing parameters can be changed dynamically. The issue here is that I don't think switching from generation mode to passthrough mode should be considered a processing parameter. 

This is not clear and in either case, we do not mention that a reset is required for switching modes.

2019-07-23 13_59_30-Xilinx Documentation Navigator 2018.3 -  https___www.xilinx.com_support_document.png

In summary, a reset is required and I will file to have the doc changed.

To work around this, use a GPIO to reset the TPG when switching between passthrough and generation mode. This is needed to clear out the pipeline when switching.

This is the method used in the HDMI example design. 

2019-07-23 13_58_26-xcoapps63_13 (xcoapps63_13 (samk)) - VNC Viewer.png

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florentw
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Registered: ‎11-09-2015

HI @thomasmurphyge 

Actually, I believe that for any version of the Test Pattern Generator IP you are expected to reset the IP when you change the configuration.

This is a HLS based IP so there are pipelines you need to reset in the background.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
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Registered: ‎11-09-2015

Hi @thomasmurphyge 

Is everything clear for you on this topic?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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thomasmurphyge
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Registered: ‎09-20-2018

Hello Florent,

The TPG PG103 December 5, 2018 version 8 doesn't describe the need to reset on all configuration changes, only on image size changes or "entire system" restart (Ch. 3, section "System Considerations"). The revision history from 7 to 8 (as would be the difference between 2018.2 and 2019.1) does not mention that enabling or disabling the AXI-S input would cause a processing error or different behavior in the new version. If the statements about changing TPG parameters is no longer correctly documented in PG103, then the guide needs to be updated. Being able to conveniently switch between the AXI-S input and internal pattern generation was very convenient in my prior testing because it reduced my software complexity.

-Thomas

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samk
Moderator
Moderator
1,274 Views
Registered: ‎10-04-2017

Hi @thomasmurphyge,

 

Here is the section from PG103, December 5, 2018. It is here to show that processing parameters can be changed dynamically. The issue here is that I don't think switching from generation mode to passthrough mode should be considered a processing parameter. 

This is not clear and in either case, we do not mention that a reset is required for switching modes.

2019-07-23 13_59_30-Xilinx Documentation Navigator 2018.3 -  https___www.xilinx.com_support_document.png

In summary, a reset is required and I will file to have the doc changed.

To work around this, use a GPIO to reset the TPG when switching between passthrough and generation mode. This is needed to clear out the pipeline when switching.

This is the method used in the HDMI example design. 

2019-07-23 13_58_26-xcoapps63_13 (xcoapps63_13 (samk)) - VNC Viewer.png

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

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thomasmurphyge
Observer
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Registered: ‎09-20-2018
Thank you for filing for this documentation improvement. I've adopted the clumsy, but necessary AXI-GPIO-as-a-reset-controller architecture for my video pipeline as is the technique across Xilinx video example designs.

-Thomas
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tgharbi2020
Contributor
Contributor
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Registered: ‎09-28-2019

Hello,

In this case, how to reset TPG through GPIO when we are running Linux on Zynq?

From userspace app, it's not possible.

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samk
Moderator
Moderator
532 Views
Registered: ‎10-04-2017

Hi @tgharbi2020,

 

This is a separate issue, please start a new topic to have the community reply.

See the forum guidelines for more information.

 

Thanks,

Sam

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Xilinx Video Design Hub
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