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guerric.mdd
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Registered: ‎12-18-2017

UHD-SDI GT documentation?

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Hello,

 

For a SDI design, I started from the smpte_uhdsdi_rx_ss audio-video example design on KCU116.

 

Where can I find documentation about the UHD-SDI GT (v1.0) IP? I googled it / docNaved it / tried documentation button from customization GUI without success. I can't find the smpte_uhdsdi_rx_ss v2.0 documentation neither (where there would be hopefully information about example design on KCU116).

I'm using Vivado 2018.1 (since it is the first release where it is publicly available).

 

In particular I'm wondering about the details of the cmp_gt_ctrl[63:0] vector.

I'm using IP with more than 1 RX/TX and I suspect I need to update the uhdsdi_gt_ctrl HDL block to feed cmp_gt_ctrl properly.

 

By the way, for UHD-SDI GT IP customization GUI in IPI, I see that labels for PLL of link 1 and beyond are not correct.

 

Any idea about the manual or guidelines about cmp_gt_ctrl?

 

Thanks,

Regards,

Guerric

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florentw
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Registered: ‎11-09-2015

Hi @guerric.mdd,

 

The updated documentation for pg289 and pg290 are online:

https://www.xilinx.com/support/documentation/ip_documentation/v_smpte_uhdsdi_tx_ss/v2_0/pg289-v-smpte-uhdsdi-tx-ss.pdf

https://www.xilinx.com/support/documentation/ip_documentation/v_smpte_uhdsdi_rx_ss/v2_0/pg290-v-smpte-uhdsdi-rx-ss.pdf

 

If everything is clear for you, please kindly close the topic by marking a reply as accepted solution.

 

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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View solution in original post

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drjohnsmith
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Registered: ‎07-09-2009

https://www.xilinx.com/support/documentation/ip_documentation/v_smpte_uhdsdi/v1_0/pg205-v-smpte-uhdsdi.pdf

 

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guerric.mdd
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Registered: ‎12-18-2017

Thanks drjohnsmith,

But the link you provide is the UHD-SDI IP documentation, not the UHD-SDI GT IP documentation. 

UHD-SDI GT IP is publicly available since Vivado 2018.1.

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drjohnsmith
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Registered: ‎07-09-2009

my appoligies

 

which chip you trying to run on ?

 

 

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guerric.mdd
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Registered: ‎12-18-2017

Kintex Ultrascale+ (on KCU116), so using GTY.

Thanks in advance!

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drjohnsmith
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Registered: ‎07-09-2009

Im guessing doc is catching up

 

would this help

 

https://forums.xilinx.com/t5/Video/SDI-over-GTY/td-p/811032

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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florentw
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Registered: ‎11-09-2015

Hi @guerric.mdd,

 

The documentation of the UHD-SDI GT will be part of the documentation for the UHD-SDI Subsystem. So @drjohnsmith was nearly pointing you to the correct reference for the doc. There won't be a separated documentation for this

 

However, the new documentation has been push online, it takes some time to be online. It should be in the pg289/pg290 in the next few days.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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guerric.mdd
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Registered: ‎12-18-2017

Hello Florent,

 

Ok, waiting for the updated pg289/pg290 then.

Thanks!

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florentw
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Registered: ‎11-09-2015

Hi @guerric.mdd,

 

The updated documentation for pg289 and pg290 are online:

https://www.xilinx.com/support/documentation/ip_documentation/v_smpte_uhdsdi_tx_ss/v2_0/pg289-v-smpte-uhdsdi-tx-ss.pdf

https://www.xilinx.com/support/documentation/ip_documentation/v_smpte_uhdsdi_rx_ss/v2_0/pg290-v-smpte-uhdsdi-rx-ss.pdf

 

If everything is clear for you, please kindly close the topic by marking a reply as accepted solution.

 

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

guerric.mdd
Participant
Participant
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Registered: ‎12-18-2017

Here they are.

Thanks Florent!

 

Unfortunately, there are no details about ports of the UHG-SDI GT IP in appendix C of RX documentation (especially mapping of cmp_gt_ctrl[63:0] and cmp_gt_sts[63:0]).

But since it is a different question I'll mark thread as solved.

Thanks. 

florentw
Moderator
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Registered: ‎11-09-2015

Hello @guerric.mdd,

 

I do not have the info right know. I have repported this to development.

 

If you feel you really need to know, create a new topic and I will try to find the answer.

 

Note: You should be able to find the informtion by looking at the generated RTL which shouldn't be encrypted

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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hoalenew
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Registered: ‎04-18-2018

Hi,

I am using the xapp1249(UHD-SDI). and configured as 6G-SDI. Can you advise how the 4:2:2 YCbCr 10-bit image per ST 2081-10 mapping mode 1 for transport on a 6G-SDI. What do I need to do with Y,C to ds3 and ds4.

Thanks

Hoa

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florentw
Moderator
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Registered: ‎11-09-2015

Hi @hoalenew,

 

This is a different question. Please create a new topic on the video board.

 

As this topic is already solved, I am closing the topic for new reply.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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