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Adventurer
Adventurer
506 Views
Registered: ‎03-17-2017

UHD-SDI GT txoutclk broken

When the UHD-SDI GT core is configured for a Line Rate of 3G-SDI the txoutclk is broken, by which I mean it is NOT connected to anything internal to the core. Here is my setup...

1. I'm running Vivado 2019.2 with the revison 2 patch applied from AR73173 here https://www.xilinx.com/support/answers/73173.html

2. This is a tx ONLY design, but there is no such option, so Duplex is selected

3. Core Config as follows

UHD-SDI GT Core Config.png

After elaboration it can be observed that there is a complete disconnect between GTHE4_CHANNEL and the intf_0_txoutclk...

txoutclk_disconnect1.pngtxoutclk_disconnect2.png

After synthesis is can also be observed that clock constraints are failing to be applied since they can't find the clock. Here is one such example...

[Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_tx_inst/*gtwiz_userclk_tx_active_*_reg}]'. ["blah/ip/sdi_gth/sdi_gth.xdc":78]

 

I have tried many different combinations of the ip core configuration settings and it seems to me that ONLY a Line Rate of 12G-SDI will result in a connected txoutclk. Although the AR patch did enable the ability to build the IP for a line rate of 3G-SDI it is currently a broken configuration, as is HD-SDI & 6G-SDI as well. Is there any way around this or is an additional patch required? 

3 Replies
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Xilinx Employee
Xilinx Employee
395 Views
Registered: ‎12-03-2019

Reproduced the issue at my End.

 

 

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Adventurer
Adventurer
377 Views
Registered: ‎03-17-2017

@mnagpal thanks for looking into this. Now that you've been able to reproduce the issue is there a chance a new patch could be deployed so that we may continue our development?

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Xilinx Employee
Xilinx Employee
134 Views
Registered: ‎12-03-2019

Hi @baf2099 ,

This is known issue and it will be fixed in the upcoming version.
As a workaround please use the 12G-SDI.

Thanks,
Manish
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