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eddylee
Observer
Observer
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Registered: ‎11-21-2017

UHD-SDI Transmitter Subsystem v2.0 IP does not output the picture.(KCU116,PG289,PG290,PG205,PG380)

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Hi,

I made a loopback design from SDI RX(UHD-SDI Receiver Subsystem v2.0) to SDI TX(UHD-SDI Transmitter Subsystem v2.0) IP with 3G SDI.
But TX does not output the picture, and RX-3GSDI side is locked with ILA verification.

The hardware environment is KCU116 board with Inrevium SDI FMC Card, which is same as in PG298.

The vivado version is 2020.2

The block design are shown below.

eddylee_0-1626311852396.png

Both RX and TX use native video mode and directly connected.

eddylee_2-1626312239994.png

The IP settings are shown below.

SDI TX IP :

eddylee_1-1626312104019.png

SDI TX IP Setting : These setting controlled by VIO.

eddylee_8-1626312890673.png

eddylee_6-1626312466794.png

 

SDI RX IP : 

eddylee_3-1626312358446.png

SDI RX IP Setting :

eddylee_10-1626313724569.png

UHD GT IP :

eddylee_4-1626312401169.png

UHD GT IP Setting :

eddylee_9-1626313555409.png

Below is the native video stream to the TX source recorded by ILA, it looks good.

The sdi_tx_err signal from TX IP output are all 0.

eddylee_7-1626312595843.png

 

Could you please provide any suggestions?

Regards,
Thank you

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ashokkum
Moderator
Moderator
98 Views
Registered: ‎04-09-2019

Hello @eddylee ,

You mentioned that you referred our loop back example design. If you seen that, the sub system IP's communicate with micro-blaze over AXI4-lite interface for register space programming. Also, If you try to extract the hierarchy of SDI RX/TX Sub System IP in the block design, you will find the VTC IP, Video Bridge and SDI TX/RX bridge IP's along with the SDI TX/RX IP's.

So, Please refer the design quickly and check it once at your end.

With Regards,

Ashok.  

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10 Replies
ashokkum
Moderator
Moderator
449 Views
Registered: ‎04-09-2019

Hello @eddylee ,

We provided the example design for KCU116, Which is Audio-Video Loop Back. It is AXI interface based. Did you try to run this example design on your board? If yes, could you please let me know, would you able to see the output video on the display. Please let me know this. Because, it confirms that your board TX pipeline  HW is good or not?

Once, we get a confirmation about HW. We will dig in more to debug this case furtherly.

With Regards,

Ashok.

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eddylee
Observer
Observer
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Registered: ‎11-21-2017

I have run the example design of KCU116 before, the SDI-TX displays color bars by default on my screen, so I think the hardware environment is fine.

 

Regards,

Thank you.

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ashokkum
Moderator
Moderator
401 Views
Registered: ‎04-09-2019

Hello @eddylee ,

Could you please check whether the Timing Reference Signals are generated by TX sub system. Also, could you please share the ILA capture of cmp_gt_ctrl and cmp_gt_sts signals, Register space of SDI RX and TX sub systems. These details would be helpful to know the PLL locks, GT Reset state and ST352 Payload generation. Based on that we will proceed to the next steps for debugging this issue.

With Regards,

Ashok.

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eddylee
Observer
Observer
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Registered: ‎11-21-2017

Hi,

Please refer attachment .ila files.

Thanks.

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eddylee
Observer
Observer
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Registered: ‎11-21-2017

Hi,

Is the waveform of .ila file OK?

Do you need other information?

 

Thanks.

 

Regards,

Eddy.

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ashokkum
Moderator
Moderator
223 Views
Registered: ‎04-09-2019

Hello @eddylee ,

I gone through the ILA captures. The cmp_gt_sts is good, all the PLL's were locked. RX side the video mode was locked and proper SDI mode was detected. So, we need to check the SAV, EAV and TRS signals alignment in TX pipeline. Could you please check those signals were generated properly (i.e. in each line these signals were generated at a constant pixel number), this can be achieved by running an internal pixel counter for each line to know the positions of these reference signals(SAV, EAV, XYZ word and TRS). Kindly check this, if these signals are misaligned, then we won't be able to see the output video on display channel.

With Regards,

Ashok.

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eddylee
Observer
Observer
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Registered: ‎11-21-2017

Hi,

Please check the sav and eav counter in .ila file.

I use pixel_cnt to count how many pixels come in from SDI-RX native video interface, then when eav and sav are insertd, reocrd the count.
the value of eav_cnt and sav_cnt are fixed in each line.

eddylee_0-1627022612556.png

 


In addition, I would like to ask the part where SDI-RX is connected to SDI-TX in the figure below.
Is this connection correct for these two IP? Or is it not allowed in this way?

eddylee_1-1627022666410.png

 

Thanks.

Regards.

Eddy

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ashokkum
Moderator
Moderator
151 Views
Registered: ‎04-09-2019

Hi @eddylee ,

Then, I hope nothing to doubt at design side. We need to check with, whether API is driving the VTC properly or not? While working with AXI Interface, API will take care of VTC programming. Whereas in Native interface, use needs to do this task on their own. The same process we are doing for HDMI designs. Could you please check the VTC programming is done properly by the drivers in VITIS.

With Regards,

Ashok.

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eddylee
Observer
Observer
137 Views
Registered: ‎11-21-2017

Hi, I did not add MicroBlaze IP and VTC IP to the block design, so my block design seems to be incorrect .

I did not implement the RTL function like VTC, so the SDI-RX and SDI-TX IP cannot be connected to each other as shown in the picture.

Is my understanding correct?

 

Thanks.

Regards.

Eddy

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ashokkum
Moderator
Moderator
99 Views
Registered: ‎04-09-2019

Hello @eddylee ,

You mentioned that you referred our loop back example design. If you seen that, the sub system IP's communicate with micro-blaze over AXI4-lite interface for register space programming. Also, If you try to extract the hierarchy of SDI RX/TX Sub System IP in the block design, you will find the VTC IP, Video Bridge and SDI TX/RX bridge IP's along with the SDI TX/RX IP's.

So, Please refer the design quickly and check it once at your end.

With Regards,

Ashok.  

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