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Visitor
Visitor
3,210 Views
Registered: ‎10-06-2011

UP sampling

Hello,

 

I use a commercial board with ADC, FPGA and DAC.

the ADC clock is 100MHz, so FPGA and DAC are also working at this rate.

 

I would like to reduce the latency of the FPGA part in working at 3 times the ADC rate (300 MHz) which should be compatible with the behavior of a Virtex4 LX160.

how to do that with simulink and system generator ?

 

I tried to put and x3 up sampling block, my function, and then a /3 down sampling block to match the DAC rate.

but the system dont want to compile and ask me to change the system generator period. thus I changed it from 10ns (100MHz) to 10ns/3.

but unfortunately, the result is completely strange and the output rate is about 20ns...

 

could you help me to setup properly system generator to achieve this x3 rate working ?

 

thanks

 

ronic

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2 Replies
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Teacher
Teacher
3,202 Views
Registered: ‎08-14-2007

Hi Ronic,

running hardware internally faster than the external clock requires the use of DCMs.

By default the sysgen multirate feature uses just clock enables, but there are also modes involving DCMs.

Hopefully one of these provides the necessary abilities for your needs.

 

But aside of this, it can not be guaranteed that your design is capable of running at these speeds.

Check the static timing report to see wether your design acheives the required speed.

 

Have a nice synthesis

  Eilert

 

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Visitor
Visitor
3,201 Views
Registered: ‎10-06-2011

thank you for your answer.

I will look at this feature

 

regards

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