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sarah77wicker
Contributor
Contributor
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Registered: ‎11-05-2018

Ultra96+PCAM 5c

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Hi everyone,

Am facing a small issue with my design. I want to implement the PCAM 5C with the Ultra96 board (ver2) and the adapter Aistarvision (ver2.1).

version of the tools : 2019.2

My PL design is composed of the MIPI_CSI2_Rx subsystem, the demosaic gamma Lut ip and a VDMA.

(after the goal would be to send the data on the display port live interface of the ps.. but am already struggeling before hand ^^')

parameter are the following: - 900Mbps for RAW10 data on 2 data lanes at 2ppc

following the datasheet of the IP the video_aclk calculated is of 90MHz, we put 100MHz and video_aclk and lite_aclk have the same source. of course Dphy_clk is 200MHz.

placed an ILA at the output of our mipi ip to measure: tlast/tdest/tready and pll_lock_out/rxbyteclkhs

the bitstream is well generated, there is a timing issue but this one is coming from the ILA (haven't really looked it in more detail)

the design is then open under vitis to programm the pipeline the steps are the following:

  • initialisation of the gpio and powerup sequence for the camera (use the port 37 for the gpio)
  • initialisation of the IIC connection and first camera check (check of the high and low address)
  • reset of the camera and configuration
  • intialisation of the mipi interface
  • reset of the IP present in the pipeline (mipi/demo/gamma/vdma)
  • configure the mipi ip for 2 lanes and enabling some of the interrupt (using the XCsiSs_Configure() function)
  • init of the following ip of the pipeline (demo and gamma)
  • set up of the interrupt for the mipi interface and start of the vdma
  • activation of the mipi interface (XCsiSs_Activate(&CsiRxSs, 1))
  • enabling the camera again
  • vdma start

as results i observe that my ips are well initialised, MIPI D-phy has INIT_DONE activated and looking at the register of MIPI csi2 i receive package. Looking at the IIC connection, this one initialize well the camera. The vdma also is well initialised and looking at my ILA on vivado, pll_out lock well and the signals are behaving like expected... the issue is: I have no data, the buffer where i send the data_lane is full with only 0.

looking on the oscilloscope at data_lane0 and 1, there is no data coming. I looked at the Mipi_CP lane this one is really low ... reading some forum it would mean that mipi is in Lp00 state but i configured it so it should be in lp11 when no data are received.

Also my registers(mipi base + offset (0x60) or offset(0x64)) tell me that i received data and the Line count and Byte count are increasing.

I tried to change the INIT_VAL of the mipi dphy thinking it might be the issue (first value 100us change to 500us), the problem is still the same.

i used the files made by Adam Tailor in his hacksterio project for the initialisation of the PCAM and added this parameter : {0x3019, 0x30} to specify that my lanes must go to the lp11 state in sleep mode.

am getting a bit stuck on this and looking forward if any of you have an idea ^^

best regards

sarah

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watari
Teacher
Teacher
639 Views
Registered: ‎06-16-2013

Hi @sarah77wicker 

 

I just ask you the following to investigate the route cause.

 

- When did you buy Vultra96 ?

- How much core current do you prepare ? (Do you supply enough core current ?)

 

As you know, latest Ultra96V2 only fix core current issue.

So, I'm not sure but I suspect this issue...

 

Best regards,

View solution in original post

7 Replies
karnanl
Xilinx Employee
Xilinx Employee
655 Views
Registered: ‎03-30-2016

Hello Sarah @sarah77wicker 

Did you solve your MIPI issue ?

We saw some issue with MIPI CSI-2 RX controller and VFB generated from Vivado 2019.2.
If not, Could you please install this patch AR73100_Vivado_2019_2_preliminary_rev2.zip to your Vivado 2019.2 ?

AR#73100  will be updated next week.
If you still see unexpected behaviour after using this patch, please share the ILA file. I will be happy to help.


Thanks & regards
Leo

watari
Teacher
Teacher
640 Views
Registered: ‎06-16-2013

Hi @sarah77wicker 

 

I just ask you the following to investigate the route cause.

 

- When did you buy Vultra96 ?

- How much core current do you prepare ? (Do you supply enough core current ?)

 

As you know, latest Ultra96V2 only fix core current issue.

So, I'm not sure but I suspect this issue...

 

Best regards,

View solution in original post

sarah77wicker
Contributor
Contributor
622 Views
Registered: ‎11-05-2018

Hi @watari and @karnanl,

I will answer to the two of you in the same message, i hope this is ok^^

@karnanlI solved, let's say, partially my problem. I was able to obtain a stream in Baremetal. It seemed that i had several error, one was that i didn't initialise Gamma Lut corretly. This one was only sending 0 as data. Now I initialised it and reduced my Line rate in Mipi csi2 IP and I can get an image.

I used partially before because i tried to migrate the design (working in Baremetal) to linux and i ended up with the error "broken pipe (32)" when i try to use yavta for making a capture.

From the information i gathered it seems that the pcam can't send RAW10 datas and if i take the driver from digilent i should configure everything for pixel data with YUV422 format... i am still working on it and will also test it with the patch you gave :)

@watarii bought the ultra96 almost a year ago in April or mai(if i recall correctly), but it was already the 2nd version.

Core current? are you meaning the supply to the board?

if this is that, I supply the board with 4A. After I saw that the adapter board for the mipi camera was laking pullup resistor. I fixed it and after that could I could see and interract with the camera (at least in  baremetal).

 

I made a small check on the I2C lane yesterday to check if the data were well sent and if in Baremetal it is well written to the address 3c of my sensor for some reason using linux the address changed and became 0x78 (not even 0x75 address of my I2C mux...) will continue to investigate on this part as well.

 

Thank you a lot for your help guys!

best regards

sarah

watari
Teacher
Teacher
602 Views
Registered: ‎06-16-2013

Hi @sarah77wicker 

 

Sorry. I just a little misunderstanding about Ultra96 issue.

Have you ever read the following URL ?

 

https://www.avnet.com/wps/wcm/connect/onesite/5fe65cc8-17e3-42cc-841f-606d5380862c/Product+Change+Notification+PCN+19003+(U96+V2).pdf?MOD=AJPERES&CVID=m.lqrMa&CVID=m.lqrMa&CVID=m.lqrMa&attachment=false&id=1579833531195&

 

This is latest PCN information.

Avnet has already modified PCB design to fix some issue which ware already discussed on Avnet's forum.

 

[Additional information]

FYI, if necessary.

 

https://www.avnet.com/opasdata/d120001/medias/docus/196/AES-ULTRA-96-V2-Errata-EN.pdf

 

Best regards,

sarah77wicker
Contributor
Contributor
543 Views
Registered: ‎11-05-2018

It works!

thanks a lot @watari i didn't know these issues, i don't think that was what was perturbing our results but will look into it a bit better.

However i have a couple of questions still, if you have time^^'

to make it works i made the following change:

-> driver is not loaded as built-in anymore but as module in petalinux kernel configuration

-> all interrupts are not connected to the axi_interrupt IP anymore but directly to the interrupt of the PS via contact IP(mipi rx interrupt and vdma interrupt)

Do you have an idea why interrupts work better is they are directly connected to the PS? I checked before when i was using the IP and the interrupt were connected: cat /proc/interrupt showed that all the interrupts were present, but now they are present and triggered.

also the capture works: yavta -c14 -f YUYV -s "$width"x"$height" -F /dev/video0

but only for the first frame and the ones after the 7th frames. I mean I have 14 captures in total but on the number 01 to 07 the capture is only green. Is there a specific reason for it? I saw that often in the explaination "how to use v4l2 drivers" yavta tool was used with the 7 first frames skipped

example:"yavta -n 3 -c10 -f UYVY -s 1920x1080 --skip 7 -F /dev/video4 "
 
best regards,
sarah
watari
Teacher
Teacher
516 Views
Registered: ‎06-16-2013

Hi @sarah77wicker 

 

>Do you have an idea why interrupts work better is they are directly connected to the PS? I checked before when i was using the IP and the interrupt were connected: cat /proc/interrupt showed that all the interrupts were present, but now they are present and triggered.

 

I have no idea to explain it.

 

>but only for the first frame and the ones after the 7th frames. I mean I have 14 captures in total but on the number 01 to 07 the capture is only green. Is there a specific reason for it?

 

I'm not sure. But I suspect frame dropped by causing V4L2 kernel driver (dma-contig) turn off cache.

It is hard to explain the detail. Sorry for inconvenient.

 

Best regards,

sarah77wicker
Contributor
Contributor
484 Views
Registered: ‎11-05-2018

Ok, thank you a lot for your answer

best regards

sarah