09-08-2020 06:12 AM
I'm new to the Ultrascale+ architecture, so I'm having some difficulties to understand the impacts/requirements of using the VCU DDR4 IP.
Is it possible for the PS to access the DDR when using the VCU DDR4 IP?
I have 3 video streams to encode using H.264/265: 2x 1080p 60fps and 1x 720p 60fps, do I need to use the VCU DDR4 IP? Could you please clarify when the use of the VCU DDR4 IP is mandatory?
My design uses a XCZU5EV.
09-13-2020 10:19 AM
Have you done PS-DDR bandwidth requirement calculations for your 3 stream encode requirement and do you have the sufficient memory available for the same? For PS DDR controller you can avail max 4Gb of RAM and in that memory you can easily fit encode operation for 2 streams of 1080p60 and 720p60.
The need of VCU PL DDR4 controller IP would come in to picture when you have high bandwidth requirement.
Can you give details about the video format you are working on for your three streams?
Xilinx offers below example for high bandwidth requirement use case where PS DDR bandiwdth is not sufficient for encode and decode operation so PL DDR4 controller is necessary.
Let me know if it helps clarify your doubts.
09-14-2020 11:46 AM
Hi @kvasantr ! Thank you for your reply!
"Have you done PS-DDR bandwidth requirement calculations for your 3 stream encode requirement", I just did it, please take a look at the attached print-screen.
I got the following from Vivado:
The project has 2GB of DDR4-3200, but actual clock is 2400MHz, thus, the DDR4 peak bandwidth is 19200MB/s. So it's seems that I don't have a bottleneck regarding PS-DDR bandwidth, right?
"Can you give details about the video format you are working on for your three streams?". This is the info. that I have:
I have one more question, but it's related to the XPE tool: how should I configure the VCU in the XPE? I can't find a way to add 3 streams on it. How should I configure it? (please take a look at the attached print-screen)
Thank you again!