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brian.trotter
Adventurer
Adventurer
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Registered: ‎11-09-2012

Undocumented sof_state & sof_state_out signals on Video Timing Controller & AXI4-Stream to Video Out IP cores

After upgrading from Vivado 2020.1 to 2020.2, the AXI4-Stream to Video Out and Video Timing Controller IP cores gained new signal: sof_state_out and sof_state, respectively. However, the documentation for these cores has not been updated to include these signals.

Can someone please provide an official explanation of these signals' behavior and required or recommended connections?

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kuroro20
Observer
Observer
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Registered: ‎02-04-2019

 Up! i'm insterested

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tschesnok
Observer
Observer
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Registered: ‎07-23-2019

Up! Yes, me too.. can I leave it unconnected??? Spent some time looking and I don't see release notes or documentation.. 

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brian.trotter
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Registered: ‎11-09-2012

Xilinx? Any help? You have released IP with undocumented I/O. I trust the Product Guides will be updated at some point, but will you please provide information here in the meantime?

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ashokkum
Moderator
Moderator
201 Views
Registered: ‎04-09-2019

Hello @brian.trotter ,

sof_state_out is basically AXI stream Video data start of frame, and it is output signal from AXI Video out bridge. It is same signal which goes to VTC to indicate AXI4-Stream Start of Frame input to VTC

Hope this helps to you. please feel free to respond if you have any further questions.

Kind Regards,

Ashok.

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brian.trotter
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Registered: ‎11-09-2012

Hi @ashokkum. I guessed as much by the names. I was hoping for more detailed information. Is the connection between the bridge and the VTC required under all conditions, certain conditions, or optional? The cores worked previously without it, so I am trying to understand what changed and exactly how it is generated and used by the cores.

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