12-07-2020 07:44 PM - edited 12-07-2020 07:45 PM
After upgrading from Vivado 2020.1 to 2020.2, the AXI4-Stream to Video Out and Video Timing Controller IP cores gained new signal: sof_state_out and sof_state, respectively. However, the documentation for these cores has not been updated to include these signals.
Can someone please provide an official explanation of these signals' behavior and required or recommended connections?
01-04-2021 07:12 AM
Xilinx? Any help? You have released IP with undocumented I/O. I trust the Product Guides will be updated at some point, but will you please provide information here in the meantime?
01-04-2021 08:44 PM
Hello @brian.trotter ,
sof_state_out is basically AXI stream Video data start of frame, and it is output signal from AXI Video out bridge. It is same signal which goes to VTC to indicate AXI4-Stream Start of Frame input to VTC
Hope this helps to you. please feel free to respond if you have any further questions.
01-08-2021 08:43 AM
Hi @ashokkum. I guessed as much by the names. I was hoping for more detailed information. Is the connection between the bridge and the VTC required under all conditions, certain conditions, or optional? The cores worked previously without it, so I am trying to understand what changed and exactly how it is generated and used by the cores.