05-15-2020 12:24 AM
I am using the native mode of the DP 1.4 RX, and I want to make it so the rx_vid_enable does not de-assert in the "active period" (as shown in https://www.xilinx.com/support/documentation/ip_documentation/v_dp_rxss1/v2_1/pg300-v-dp-rxss1.pdf, pg.54 figure 13 of the PG300). I am guessing that I need to program my PLL which generates the rx_vid_clk using the mvid and nvid values. However, mvid is changing. How fast do I need to react to the changes in mvid for this to occur? I can not imagine I can be fast enough, so what is the correct way to do this?
05-17-2020 08:29 PM
I'm sure that you need to implement clock tracking mechanism with mvid and nvid.
However it has some know-how to adjust/track clock frequency without any error.
But, would you try it ?
05-18-2020 03:39 AM
Xilinx has not done any characterization on outputting Native video directly from the Displayport 1.4 RX Subsystem Core. So we do not have any data that I can share.
However this is my understanding of the Displayport specification: