Use of mvid and nvid values DP 1.4 RX Design

[vincenttrinh]

Hi,

I am using the native mode of the DP 1.4 RX, and I want to make it so the rx_vid_enable does not de-assert in the "active period" (as shown in https://www.xilinx.com/support/documentation/ip_documentation/v_dp_rxss1/v2_1/pg300-v-dp-rxss1.pdf, pg.54 figure 13 of the PG300).  I am guessing that I need to program my PLL which generates the rx_vid_clk using the mvid and nvid values.  However, mvid is changing.  How fast do I need to react to the changes in mvid for this to occur?  I can not imagine I can be fast enough, so what is the correct way to do this?

Thank you,

Vincent

[watari]

Hi @vincenttrinh 

I'm sure that you need to implement clock tracking mechanism with mvid and nvid.

However it has some know-how to adjust/track clock frequency without any error.

But, would you try it ?

Best regards,

[florentw]

Hi @vincenttrinh 

Xilinx has not done any characterization on outputting Native video directly from the Displayport 1.4 RX Subsystem Core. So we do not have any data that I can share.

However this is my understanding of the Displayport specification:

• If the source is transmitting in synchronous mode, MVID and NVID will not change over time. So this is an easy implementation if you have a PLL which can support the 24 bits precision of MVID and NVID
• If the source is transmitting in asynchronous mode, MVID and NVID can change every line during the horizontal blanking period. So you might have less than a blanking period to do the update.
  • With that said, you might implement a small FIFO and check how it is filling up. Then you use rounded value of MVID and NVID (round up or truncate) depending if you are emptying the FIFO too quickly or too slowly
  • Also, the specification mentions that depending on the jitter requirement of your application, only rounding the values can help