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Contributor
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Registered: ‎01-27-2019

Using frame buffer vs vdma for 4k hdmi passthrough

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I would like to ask further questions after reading the following 2 posts on handling 4K videos

1. https://forums.xilinx.com/t5/Video-and-Audio/Timing-parameters-for-4K-UHD-3840-x-2160-resolution/td-p/850215

@hariprasadbstated that using framebuffer is better than vdma.

2.https://forums.xilinx.com/t5/Video-and-Audio/VDMA-vs-Video-FrameBuffer-R-W-IP-Cores/td-p/842132

@florentwstated that frame buffer and vdma have the same functionality and ..

"You could do write only with the VDMA also.However I recommend to use the frame buffer as it seems to slowly replace the VDMA (better for Linux, better performance...)"

Can anyone elaborate what is the recommended way to handle 4k hdmi passthrough?

which of the following are the best practices?

a) hdmi in -> framebuffer -> ip -> framebuffer -> hdmi out

b) hdmi in -> framebuffer -> ip -> vdma -> hdmi out

c) hdmi in -> vdma > ip > framebuffer -> hdmi out

 

 

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Registered: ‎11-09-2015

Hi @dr.elichan 

Please check my comment in the first topic you mentioned

https://forums.xilinx.com/t5/Video-and-Audio/Timing-parameters-for-4K-UHD-3840-x-2160-resolution/m-p/913287/highlight/true#M22806

@florentw  wrote:

HI @hariprasadb,

Thank you for sharing.

To work with higher resolution we need to use Frame buffer read & write IPs. Even all xilinx example designs for video supporting 4K comes with frame buffer IPs. I did not get any confirmation saying that VDMA doesn't support more than 1080p. 

> This is incorrect. The VDMA can be used for 4K. For example, the Displayport 1.2 example design on KCU105 or KC705 is built with the VDMA and can go up to 4K

 

 


 

If you are doing baremetal, both can be used. The main difference on how they work is that for the VDMA the buffers are programmed in the HW so the IP takes care of switching between the buffers. While the video frame buffer you have an interrupt generated at the end of each frame and the SW takes care of switching between frame buffers. But the AXI VDMA can do this as well.

One other difference is that the AXI VDMA is writting in memory on the exact same way it receiving the data. While the Video frame buffer reorganize the data. This is an advantage when running under linux as it allows to support many V4l2 formats. But this is not an advantage under baremetal

The following AR give more details:

https://www.xilinx.com/support/answers/72543.html 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @dr.elichan 

Please check my comment in the first topic you mentioned

https://forums.xilinx.com/t5/Video-and-Audio/Timing-parameters-for-4K-UHD-3840-x-2160-resolution/m-p/913287/highlight/true#M22806

@florentw  wrote:

HI @hariprasadb,

Thank you for sharing.

To work with higher resolution we need to use Frame buffer read & write IPs. Even all xilinx example designs for video supporting 4K comes with frame buffer IPs. I did not get any confirmation saying that VDMA doesn't support more than 1080p. 

> This is incorrect. The VDMA can be used for 4K. For example, the Displayport 1.2 example design on KCU105 or KC705 is built with the VDMA and can go up to 4K

 

 


 

If you are doing baremetal, both can be used. The main difference on how they work is that for the VDMA the buffers are programmed in the HW so the IP takes care of switching between the buffers. While the video frame buffer you have an interrupt generated at the end of each frame and the SW takes care of switching between frame buffers. But the AXI VDMA can do this as well.

One other difference is that the AXI VDMA is writting in memory on the exact same way it receiving the data. While the Video frame buffer reorganize the data. This is an advantage when running under linux as it allows to support many V4l2 formats. But this is not an advantage under baremetal

The following AR give more details:

https://www.xilinx.com/support/answers/72543.html 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post