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Observer
Observer
888 Views
Registered: ‎05-18-2018

Utilizing Xilinx Video IP

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I want to set up a basic image processing chain for Zynq but it seems I am lacking some basic understanding.

So far I wrote all the IP by myself. A pattern generator, a memory interface and a timing controller for the display output. I did this to understand how it works in principle.

Now I want to utilize some of the Xilinx IP, like the pattern generator, video mixter, the vpss, etc since they are much more capable. But all these IPs offer only one clock connection.

In my current design the video timing controller predefines the AXI stream frequency to 148.5 MHz because of full HD. The ARM does not support this frequency for AXI memory access. But I can not run the Xilinx IP with two different clock domains.

How is this intended to work? What am I missing? The example designs contain a microblaze, but I'd rather stay with the ARM core.

Thank you for help!

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Scholar
Scholar
866 Views
Registered: ‎08-07-2014

m@rx,

How is this intended to work? What am I missing?

As I have understood it, your custom IP is operating at clk_x while the Zynq subsystem is operating at clk_y.

In this situation you need an independent clock AXI FIFO between the Zynq subsystem and your IP.

Fortunately Xilinx provides such an IP. See the FIFO Generator v13.1 LogiCORE IP Product Guide (PG057) - Xilinx

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FPGA enthusiast!
All PMs will be ignored
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Scholar
Scholar
867 Views
Registered: ‎08-07-2014

m@rx,

How is this intended to work? What am I missing?

As I have understood it, your custom IP is operating at clk_x while the Zynq subsystem is operating at clk_y.

In this situation you need an independent clock AXI FIFO between the Zynq subsystem and your IP.

Fortunately Xilinx provides such an IP. See the FIFO Generator v13.1 LogiCORE IP Product Guide (PG057) - Xilinx

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------

View solution in original post

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Moderator
Moderator
827 Views
Registered: ‎11-09-2015

Hi m@rx,

Most Xilinx designs will use a VDMA or a frame buffer to separate the AXI4-Stream interface to the native video interface. But as @dpaul24 mentioned you can also simply use a FIFO.

If everything is clear for you please kindly mark @dpaul24's reply as accepted solution to close the topic.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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