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joe306
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Registered: ‎12-07-2018

VCK190 Page 50 HDMI I2C Translator

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Hello, I am looking on page 50 of the VCK190 Schematics I  have a question about signals HDMI_TX_SNK_SCL and HDMI_TX_SNK_SDA which go from U43 to U49 and to P2A.

I do not understand why these signals are going to U49? There is no connections on U49-1 and U49-2?

Last, did the design choose not use the ESD pins on U49 and choose to use separate TVS EDS diodes on the HDMI TX diff pairs?

Thank you

Joe

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xud
Xilinx Employee
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Registered: ‎08-02-2007

@joe306 

Glad that you understand that no I2C level shifting for U70.

Can you close this thread by marking most suitable reply as accepted solution?

Thanks,

Xu

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anatoli
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Registered: ‎06-14-2010

Hello @joe306 ,

Thanks for reporting this issue to us.

We are currently checking with the HDMI expert to see if we can confirm if it’s potentially a typo in schematic or not? I will update you once i hear back from the HDMI experts.

Hope this is OK with you.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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joe306
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Hello, thanks for responding to my post. Can you also ask why he/she used separate TVS diodes instead of using the ESD pins on U49?

 

Thank you

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joe306
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Hello, have you heard back from the designer on this question?

Thank you

Joe

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anatoli
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Hello @joe306 ,

I have just heard back from the boards team on this matter. This implementation has been in place since Zynq Ultrascale, with no issues. They probably used the companion chip for I2C I2C signals instead of discrete TVS diodes to reduce component count. Discrete TVS diodes were used on the HDMI2.0 data lanes. 

Hope this helps. 

If you have any further questions, please let us know.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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joe306
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Hello, thank you for getting back with me. Can you please look at U49 and tell my why they connected pins 7 and 8 but pins 1 and 2 are not connected. Correct me if I'm wrong here but U49 is a Voltage Translator so if you connected to pins 7 and 8  which are in the B side then pins 1 and 2 should be the other side of the voltage translator. Does not make any sense and that is why I'm asking.

I see the same thing done on the ZCU106 board page 50.

HDMI_TX.jpg

I understand the designer chose to use discrete TVS diodes, but this issue with the I2C signals, it does not make any sense. Why route to U49 for I2C Level Shifting if you are not doing to Level Shift?

 

Thank you very much,

Joe

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anatoli
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Registered: ‎06-14-2010

Hello @joe306 ,

I've moved this to the HDMI (well, Video&Audio) forum board, as HDMI experts are better to handle this request, instead of board and Kits experts.

@girishm , @xud can you please advice further on this matter? Thanks in advance.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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If starting with Versal, take a look at our Versal Design Process Hub and our
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joe306
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Thank you very much

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xud
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Registered: ‎08-02-2007

@joe306 

The extra chip is for ESD purposes. I2C is connected to DP159, so it is not required for I2C to shift the levels.

 

joe306
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Hello, I don't understand why U70 pins 1 and 2 are not connected?

Are you level shifting the I2C from DP159 to the HDMI connector?

Why connected the HDMI to U70 pins 7 and 8 if you are not going to connect to pins 1 and 2?

Thank you

Joe

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xud
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Registered: ‎08-02-2007

@joe306 

U70 is only used for ESD purpose on I2C,  that's why pin 1 and 2 are connected, as there are TVS EDS diodes.

But level shift is not needed, which is disabled by LS_OE, so pins 7 and 8 are not connected.

 

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joe306
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I'm confused if you look at U70 pins 1 and 2 have NC (no connects).

Pins 7 and 8 are connected. Are pins 7 and 8 used for ESD?

 

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xud
Xilinx Employee
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Registered: ‎08-02-2007

@joe306 

So you think pin 1 and 2 should be used, rather than pins 7 and 8? Let me double check this, and then get back to you.

xud_0-1616419789365.png

 

In the meantime, I checked datasheet, the SCL_B, SDA_B, CEC_B pins also feature reverse current blocking when the system is powered off.

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joe306
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Hello, I'm only asking for you to look at the ZCU106 schematics page 50. U70 pins 1 and 2 are not being used, they are NC, no connects.

Pins 7 and 8 are connected only for ESD purposes.

I understand now, there is no I2C level shifting.

Joe

 

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xud
Xilinx Employee
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Registered: ‎08-02-2007

@joe306 

Glad that you understand that no I2C level shifting for U70.

Can you close this thread by marking most suitable reply as accepted solution?

Thanks,

Xu

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