VCU Sync IP

[tharvid]

Hi! I have some questions about the VCU Sync IP used for xilinx low latency mode.

In PG252 i can only see described that the Sync IP should be configured as "encoder mode", is there any case when it should be set to "decoder mode"?

If xilinx low latency mode is used for decoding only, is the Sync IP needed at all and if so, why?

I am also wondering about the block diagrams Figure 37 and figure 38 in PG252 showing Sync IP connections in single stream and four-strem encoder modes. Is there any particular reason that the AXI Interconnects are placed as they are, with two serially connected in the four-stream case and the other way in the single-stream case? these examples only made me confused.

Best regards, Thomas

[kvasantr · Accepted solution]

Hello @tharvid 

The option for decoder mode in sync IP is redundant and it will be removed soon from the next version of IP.

Now regarding Sync IP for Decoder; it is confirmed to be removed and not a valid use case.

The reason is that Sync IP wouldn’t bring any latency improvement; currently SW waits half a frame before sending the buffer to the Display, so Sync IP isn’t needed and will never block the Display from the decoded frame.

Please go through page number 146-147 for software flow when Xilinx low latency mode is selected.

https://www.xilinx.com/support/documentation/ip_documentation/vcu/v1_2/pg252-vcu.pdf

with regards

Kunal