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evatrostaz
Participant
Participant
578 Views
Registered: ‎07-13-2020

VCU and gstreamer multifilesrc - framerate related question

Hi,

I have ZCU106 board and usb camera which is not recognized by v4l2, but with camera drivers i can capture single frames to PS RAM buffer.
My theoretical pipeline look like this

Frame buffer (PS RAM) - > HLS Kernel (for example Vitis Vision krnl) -> save files to ramdisk as .png -> Gstreamer multifilesrc with usage of HW VCU (h.264 encode) -> stream via udp/rtp

My question: Is it possible to do it like that? Gstreamer allows to set framerate as you like, but configuring VCU IP Core only allows to set fixed framerates. So i'm only allowed to use 15,30,45 and 60 in Gstreamer pipeline?

BTW. Can i add VCU IP Core in Vitis manners and start it like kernel so i can change FPS and resolution depending on variables?

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kvasantr
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Registered: ‎04-12-2017

Hello @evatrostaz 

First of all VCU IP is not supported under Vitis. It's supported only under petalinux.

But we have two examples where we have incorporated Vitis Vision libraries and AI libraries along with VCU.

You can refer to them to check about the feasibility of your pipeline.

https://github.com/Xilinx/Embedded-Reference-Platforms-User-Guide

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/689176704/Zynq+UltraScale+MPSoC+VCU+Single+Sensor+ROI+2020.1

regards

Kunal

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evatrostaz
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Registered: ‎07-13-2020

To be clear i'm using Vitis, Vivado and Petalinux 2019.2 on Ubuntu 18.04.01

I tried to include VCU in my design (which is just base for Vitis Acceleration platform and works fine) just like in pg252, but it didn't work. Instructions in Sec. I/Ch.6 are unclean, there are mismatches between text and images. Boot freezed after xvcu_probed: Probed successfull. There was error about core_enc clock and reset not connected to gpio.

Next thing was to try ZCU106 BSP, it works fine.

So i tried to customize ZCU106 BSP. But sadly during boot this was lastest displayed msg:

[    6.910285] xilinx-vcu xilinx-vcu: Could not get core_enc clock
[    6.928816] VCU PLL: enable
[    6.932582] xilinx-vcu xilinx-vcu: xvcu_probe: Probed successfull

 

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watari
Professor
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Registered: ‎06-16-2013

Hi @evatrostaz 

 

Would you share picture of BD ?

Also, make sure clock setting and connection on enc port of VCU.

If it's difficult, would you share device tree, too ?

 

Best regards,

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evatrostaz
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Registered: ‎07-13-2020

BD tcl file in attachments,

pl.dtsi where vcu is defined:

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version:  
 * Today is: Thu Sep 10 09:05:35 2020
 */


/ {
	amba_pl: amba_pl@0 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges ;
		vcu_0: vcu@a0000000 {
			#address-cells = <2>;
			#clock-cells = <1>;
			#size-cells = <2>;
			clock-names = "pll_ref", "aclk", "vcu_core_enc", "vcu_core_dec", "vcu_mcu_enc", "vcu_mcu_dec";
			clocks = <&misc_clk_0>, <&zynqmp_clk 71>, <&vcu_0 1>, <&vcu_0 2>, <&vcu_0 3>, <&vcu_0 4>;
			compatible = "xlnx,vcu-1.2", "xlnx,vcu";
			interrupt-names = "vcu_host_interrupt";
			interrupt-parent = <&gic>;
			interrupts = <0 89 4>;
			ranges ;
			reg = <0x0 0xa0040000 0x0 0x1000>, <0x0 0xa0041000 0x0 0x1000>;
			reg-names = "vcu_slcr", "logicore";
			reset-gpios = <&gpio 78 0>;
			encoder: al5e@a0000000 {
				compatible = "al,al5e-1.2", "al,al5e";
				interrupt-parent = <&gic>;
				interrupts = <0 89 4>;
				reg = <0x0 0xa0000000 0x0 0x10000>;
			};
			decoder: al5d@a0020000 {
				compatible = "al,al5d-1.2", "al,al5d";
				interrupt-parent = <&gic>;
				interrupts = <0 89 4>;
				reg = <0x0 0xa0020000 0x0 0x10000>;
			};
		};
		misc_clk_0: misc_clk_0 {
			#clock-cells = <0>;
			clock-frequency = <33330000>;
			compatible = "fixed-clock";
		};
	};
};

 

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evatrostaz
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Registered: ‎07-13-2020

OK, solved it. I was using only encoding part of VCU and petalinux DTG generated wrong pl.dtsi.
Fixed it according to this

 

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