06-24-2020 11:31 PM - edited 06-24-2020 11:34 PM
I am trying video decoder with PL DDR (VCU DDR4 IP). It is said that the PS DDR is the bottleneck. So I try the 2 use cases using the similar command:
gst-launch-1.0 --gst-debug-level=2 filesrc location=/media/card/video_bbb.mp4 ! qtdemux ! h264parse ! queue ! omxh264dec internal-entropy-buffers=7 ! queue max-size-bytes=0 ! v4l2video2convert output-io-mode=2 capture-io-mode=2 disable-passthrough=1 import-buffer-alignment=true ! fpsdisplaysink name=fpssink text-overlay=false video-sink="fakesink sync=false" sync=false -v where the input video is 4k@30fps
Measurement for PS DDR use case:
/GstPipeline:pipeline0/GstFPSDisplaySink:fpssink: last-message = rendered: 675, dropped: 0, current: 49.02, average: 48.92
For PL DDR use case
/GstPipeline:pipeline0/GstFPSDisplaySink:fpssink: last-message = rendered: 38, dropped: 0, current: 36.02, average: 36.55 /GstPipeline:pipeline0/GstFPSDisplaySink:fpssink: last-message = rendered: 57, dropped: 0, current: 36.04, average: 36.38
I applied the QoS but not sure if it's correct or not.
It seems that I am doing something wrong but could not know how to proceed as there is little documentation on this.
Could you please help?
06-29-2020 03:11 PM
06-29-2020 03:11 PM
10-01-2020 01:51 AM
We have a problem in our design. We are going to use PL DDR for Encoding/Decoding as well. We can write/read to/from PL DDR through PORT3,4 of this IP core(vcu ddr4 controller). However, when vcu wants to start encoding/ decoding it crashes. I just wanted to make sure about the hardware configuration whether you have used a GPIO reset to control the start of vcu or not? because Xilinx have used a GPIO pin for controlling reset pin of vcu in their reference design.
10-01-2020 11:51 AM
Thanks for your reply. As I mentioned a gpio to VCU reset input. There is a gpio connected to reset of VCU to have a control over it when it can start