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peakpeak
Adventurer
Adventurer
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Registered: ‎03-31-2020

VCU decode PL DDR performance issue

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I am trying video decoder with PL DDR (VCU DDR4 IP). It is said that the PS DDR is the bottleneck. So I try the 2 use cases using the similar command:

gst-launch-1.0 --gst-debug-level=2 filesrc location=/media/card/video_bbb.mp4 ! qtdemux ! h264parse ! queue ! omxh264dec internal-entropy-buffers=7 ! queue max-size-bytes=0 ! v4l2video2convert output-io-mode=2 capture-io-mode=2 disable-passthrough=1 import-buffer-alignment=true ! fpsdisplaysink name=fpssink text-overlay=false video-sink="fakesink sync=false" sync=false -v

where the input video is 4k@30fps

Measurement for PS DDR use case:

/GstPipeline:pipeline0/GstFPSDisplaySink:fpssink: last-message = rendered: 675, dropped: 0, current: 49.02, average: 48.92

For PL DDR use case

/GstPipeline:pipeline0/GstFPSDisplaySink:fpssink: last-message = rendered: 38, dropped: 0, current: 36.02, average: 36.55
/GstPipeline:pipeline0/GstFPSDisplaySink:fpssink: last-message = rendered: 57, dropped: 0, current: 36.04, average: 36.38

I applied the QoS but not sure if it's correct or not.

It seems that I am doing something wrong but could not know how to proceed as there is little documentation on this.

Could you please help?

 

 

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watari
Teacher
Teacher
429 Views
Registered: ‎06-16-2013

Hi @peakpeak 

 

Would you try 3, 7, 9 and 10 on the following document ?

 

https://www.xilinx.com/support/documentation/ip_documentation/vcu/v1_2/pg252-vcu.pdf#page=311

 

Best regards,

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4 Replies
watari
Teacher
Teacher
430 Views
Registered: ‎06-16-2013

Hi @peakpeak 

 

Would you try 3, 7, 9 and 10 on the following document ?

 

https://www.xilinx.com/support/documentation/ip_documentation/vcu/v1_2/pg252-vcu.pdf#page=311

 

Best regards,

View solution in original post

embedded
Advisor
Advisor
314 Views
Registered: ‎06-09-2011

Hi @peakpeak,

We have a problem in our design. We are going to use PL DDR for Encoding/Decoding as well. We can write/read to/from PL DDR through PORT3,4 of this IP core(vcu ddr4 controller). However, when vcu wants to start encoding/ decoding it crashes. I just wanted to make sure about the hardware configuration whether you have used a GPIO reset to control the start of vcu or not? because Xilinx have used a GPIO pin for controlling reset pin of vcu in their reference design.

 

Thanks,
Hossein
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peakpeak
Adventurer
Adventurer
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Registered: ‎03-31-2020

Hi @embedded 

Which VCU's port are you mentioning? I do not use any GPIO to connect to VCU IP.

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embedded
Advisor
Advisor
285 Views
Registered: ‎06-09-2011

Hi,

Thanks for your reply. As I mentioned a gpio to VCU reset input. There is a gpio connected to reset of VCU to have a control over it when it can start

 

Thanks,
Hossein
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