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clivewmwalker
Adventurer
Adventurer
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Registered: ‎03-21-2013

VCU low latency multistream channel limitation

Hello

There seems to be an arbitrary hard limit on the number of low-latency encoded streams that can be decoded by the VCU. It is currently not possible to decode more than 2 of these streams simultaneously, regardless of resolution. When do Xilinx plan to resolve this issue?

Thanks

Clive

 

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watari
Teacher
Teacher
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Registered: ‎06-16-2013

Hi @clivewmwalker 

 

Did you use VCU DDR4 Controller ?

I'm not sure. But it's one of solution to resolve band width issue from Xilinx.

 

Best regards,

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clivewmwalker
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Adventurer
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Registered: ‎03-21-2013

DDR bandwidth issue? I am sure this won't be an issue at lower resolutions. If there's a resolution limitation then I would prefer to hear about that, rather than imposing an arbitrary restriction on the number of channels that can be supported.

But I'm curious... did Xilinx actually mention a DDR bandwidth issue for low-latency decoding? 

Oh... and no I am not using the VCU DDR4 Controller.

Thanks

 

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