07-21-2020 04:19 PM - edited 07-21-2020 04:23 PM
There seems to be an arbitrary hard limit on the number of low-latency encoded streams that can be decoded by the VCU. It is currently not possible to decode more than 2 of these streams simultaneously, regardless of resolution. When do Xilinx plan to resolve this issue?
07-21-2020 04:41 PM - edited 07-21-2020 04:43 PM
DDR bandwidth issue? I am sure this won't be an issue at lower resolutions. If there's a resolution limitation then I would prefer to hear about that, rather than imposing an arbitrary restriction on the number of channels that can be supported.
But I'm curious... did Xilinx actually mention a DDR bandwidth issue for low-latency decoding?
Oh... and no I am not using the VCU DDR4 Controller.
07-21-2020 06:41 PM
Refer the following URLs.
BTW, did you set proper parameter for QoS ?