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Visitor
Visitor
346 Views
Registered: ‎07-21-2020

VDMA Design to read RGB video data

Hi Team,

I need to design a video capture system to capture RGB video in 5:6:5 data per pixel.

I had 8 data lines input. 8 bit data per cycle.

i need to use Video in to AXI stream IP block. and i need to save this data in proper manner to the frame buffer by using VDMA. How i can make the design to do this.

I there any example design or some design document there, please share.

How many clock cycles required to capture such a pixel. is it required to use 3 clock cycles per pixel. how i can design,

As i am a beginner here, please help me

Regards

Shankar

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6 Replies
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Visitor
Visitor
305 Views
Registered: ‎07-21-2020

Hi,
Please Reply...
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Observer
Observer
279 Views
Registered: ‎05-28-2020

Hi @Shankar ,
Can you give a few more information, like some kind of block diagram? So that, we could understand that what you are actually trying to implement.
Well, as my understanding, if you are trying to capture RGB565 video data from AXI4-streaming interface, then you cannot achieve that.
Yes, you can use VDMA. But before that I would recommend that you first get the knowledge about Streaming Video Formats and Memory Video Formats. Because,the video data you are trying to capture, i.e. RGB565, is one of memory video formats.

And I also recommend to use Frame Buffer Read/Write IP rather than VDMA IP.
Both the cores have same functionality. However, Frame Buffer Read/Write IP provides better performance and supports reading and writing a variety of video formats.
For more information, you can visit PG278 .

I hope, It might help you to figure out the design you are trying to.

Kind Regards,

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Visitor
Visitor
255 Views
Registered: ‎07-21-2020

Hi Team,

I try to implement this thing using Video in to AXI Stream IP core. I am facing some other errors. but i am not able to unterstand what is the issue in design.

I am including the images.

err1.JPGerr2.JPGerrorBD Diagram.jpg

Please help me to solve the issue

Regards,

Shankar

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Teacher
Teacher
239 Views
Registered: ‎06-16-2013

Hi @Shankar 

 

Did you create clock constraint by "create_clock" command on vid_io_in_clk port ?

 

It seems clock constraint issue.

Make sure it.

 

Best regards,

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Moderator
Moderator
184 Views
Registered: ‎11-09-2015

HI @Shankar 

It seems that you are not using a clock capable input for your clock. This is why the tool is giving you an error


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
80 Views
Registered: ‎11-09-2015

HI @Shankar 

Do you have any update on this? Were you able to solve your issue?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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