03-23-2019 12:09 PM
Hi,
I have a VDMA core connected to the output from a Test pattern generator through a subset convertor. The output goes to an axi4 stream to video out core. However when I try to initialise the VDMA core in the SDK it fails when trying to initialise the read channel. It fails even if i run just the imported vdma setup and self test example. The section below fails in XAxiVdma_CfgInitialize.
XAxiVdma_ChannelInit(RdChannel);
XAxiVdma_ChannelReset(RdChannel);
Polls = INITIALIZATION_POLLING;
while (Polls && XAxiVdma_ChannelResetNotDone(RdChannel)) {
Polls -= 1;
}
if (!Polls) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Read channel reset failed %x\n\r",
(unsigned int)XAxiVdma_ChannelGetStatus(RdChannel));
return XST_FAILURE;
}
Below is the values of the read channel and the vdma setup in vivado:
Thanks!
04-15-2019 09:49 AM
Sorry for the late reply,
I've got it working now and the only change I made was to set the FSync option on the write to tuser rather than fsync.
From this link : https://forums.xilinx.com/t5/Welcome-Join/VDMA-read-channel-Fsync-options/td-p/712036 I think I had the core incorrectly set up with the VTC fsync but im not really sure what the change I made means if someone could enlighten me?
Thanks
03-25-2019 07:59 AM
HI @tconlon03 ,
What message are you getting in the UART?
It might be that your VDMA is not getting out of reset. Thus you might also check the connection you made in your vivado design.
Regards,
04-08-2019 01:03 AM
Hi @tconlon03 ,
Do you have any updates on this? Were you able to solve your issue?
If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)
If this is not solved/answered, please reply in the topic giving more information on your current status.
Thanks and Regards,
04-15-2019 09:49 AM
Sorry for the late reply,
I've got it working now and the only change I made was to set the FSync option on the write to tuser rather than fsync.
From this link : https://forums.xilinx.com/t5/Welcome-Join/VDMA-read-channel-Fsync-options/td-p/712036 I think I had the core incorrectly set up with the VTC fsync but im not really sure what the change I made means if someone could enlighten me?
Thanks
04-16-2019 01:10 AM
HI @tconlon03 ,
If you have fsync selected on VTC fsync, this means that you need to have the fsync from the vtc connected to the VDMA to indicate when you want the VDMA to start reading.
If you are using tuser, you do not need any external signal
Regards