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Visitor
Visitor
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Registered: ‎10-10-2018

VDMA SDK setup fails at read channel initialisation

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Hi,

I have a VDMA core connected to the output from a Test pattern generator through a subset convertor. The output goes to an axi4 stream to video out core. However when I try to initialise the VDMA core in the SDK it fails when trying to initialise the read channel. It fails even if i run just the imported vdma setup and self test example.  The section below fails in XAxiVdma_CfgInitialize.

 

              XAxiVdma_ChannelInit(RdChannel);

              XAxiVdma_ChannelReset(RdChannel);

Polls = INITIALIZATION_POLLING;

              while (Polls && XAxiVdma_ChannelResetNotDone(RdChannel)) {

                     Polls -= 1;

              }

              if (!Polls) {

                     xdbg_printf(XDBG_DEBUG_ERROR,

                         "Read channel reset failed %x\n\r",

                         (unsigned int)XAxiVdma_ChannelGetStatus(RdChannel));

                     return XST_FAILURE;

              }

 

Below is the values of the read channel and the vdma setup in vivado:

 

Thanks!

read channel.pngvdma_gui1.pngvdma_gui2.png

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Visitor
Visitor
1,675 Views
Registered: ‎10-10-2018

Sorry for the late reply,

I've got it working now and the only change I made was to set the FSync option on the write to tuser rather than fsync.

From this link : https://forums.xilinx.com/t5/Welcome-Join/VDMA-read-channel-Fsync-options/td-p/712036 I think I had the core incorrectly set up with the VTC fsync but im not really sure what the change I made means if someone could enlighten me?

Thanks

 

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Moderator
Moderator
1,767 Views
Registered: ‎11-09-2015

HI @tconlon03 ,

What message are you getting in the UART?

It might be that your VDMA is not getting out of reset. Thus you might also check the connection you made in your vivado design.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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1,709 Views
Registered: ‎11-09-2015

Hi @tconlon03 ,

Do you have any updates on this? Were you able to solve your issue?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
1,676 Views
Registered: ‎10-10-2018

Sorry for the late reply,

I've got it working now and the only change I made was to set the FSync option on the write to tuser rather than fsync.

From this link : https://forums.xilinx.com/t5/Welcome-Join/VDMA-read-channel-Fsync-options/td-p/712036 I think I had the core incorrectly set up with the VTC fsync but im not really sure what the change I made means if someone could enlighten me?

Thanks

 

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Moderator
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Registered: ‎11-09-2015

HI @tconlon03 ,

If you have fsync selected on VTC fsync, this means that you need to have the fsync from the vtc connected to the VDMA to indicate when you want the VDMA to start reading.

If you are using tuser, you do not need any external signal

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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