cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Newbie
Newbie
282 Views
Registered: ‎06-23-2020

VDMA for high fps, low res video

Jump to solution

The VDMA 6.3 datasheet has a table (2-3) listing maximum achievable frame rates for standard HD (presumably 1920x1080) resolution video for different data widths. For example for a data width of 256 bits (which our design uses) this table lists a measured frame rate of 500 fps.

It is reasonable to use this data to calculate achievable frame rates for much lower resolutions? In the above example, 1920x1080x24 bitsx500 fps = 3.11 GByte/second. Does this mean the VDMA can stream e.g. 640x512x12 bit video (which comes in at 491,520 bytes per frame) at 6300 fps? Or is this too naive an approach, and does the VDMA IP have other limitations?

Thanks in advance,

Jeroen

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Scholar
Scholar
255 Views
Registered: ‎03-28-2016

@jeroen94708 

The VDMA is just one part of the overall memory system.  There are a number of factors that will determine your maximum sustained throughput.  What you have outlined is a good place to start, but think of it as a "theoretical" maximum and don't just assume that you will be able to achieve that level of throughput.

In designing your memory subsystem, use the widest path you can at each link in the system and the faster the clock the better.  Keep in mind that you can typically clock the AXI infrastructure with a faster clock than your system clock that is used to clock the AXIS ports on the VDMA.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

View solution in original post

2 Replies
Highlighted
Scholar
Scholar
256 Views
Registered: ‎03-28-2016

@jeroen94708 

The VDMA is just one part of the overall memory system.  There are a number of factors that will determine your maximum sustained throughput.  What you have outlined is a good place to start, but think of it as a "theoretical" maximum and don't just assume that you will be able to achieve that level of throughput.

In designing your memory subsystem, use the widest path you can at each link in the system and the faster the clock the better.  Keep in mind that you can typically clock the AXI infrastructure with a faster clock than your system clock that is used to clock the AXIS ports on the VDMA.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

View solution in original post

Highlighted
Newbie
Newbie
236 Views
Registered: ‎06-23-2020

Thank you, all that is clear. I was just wondering if the VDMA IP has any inherent limitations that would make it unsuitable for use with very high framerates. I gather from your reply that this is not the case, so that answers my question.

Thanks!

Jeroen

 

0 Kudos