cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mkooli
Adventurer
Adventurer
5,743 Views
Registered: ‎04-14-2017

VDMA project

Jump to solution

Hi,

I create a project to display frames generated by a TPG via VGA outputs, I succeeded  displaying frames  (below the 1st design):1.PNG

But when I add a VDMA between the "TPG "and the "Axi stream to video out" I have nothing displayed in the screen but I have signals in the TPG output and the Vdma output (below my design and the signals):

2.PNG

3.PNG

 

Please I want to know what 's the error !?

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
xud
Xilinx Employee
Xilinx Employee
8,890 Views
Registered: ‎08-02-2007

@mkooli Glad to see you have resolved the problem. here are a list of patterns you can test with.

The software code is similar to COLOR_BARS and TARTAN. 

 

At HW side,  you need to ensure the associated options are checked in TPG GUI : 

XTPG_BKGND_H_RAMP = 1,
XTPG_BKGND_V_RAMP,
XTPG_BKGND_TEMPORAL_RAMP,
XTPG_BKGND_SOLID_RED,
XTPG_BKGND_SOLID_GREEN,
XTPG_BKGND_SOLID_BLUE,
XTPG_BKGND_SOLID_BLACK,
XTPG_BKGND_SOLID_WHITE,
XTPG_BKGND_COLOR_BARS,
XTPG_BKGND_ZONE_PLATE,
XTPG_BKGND_TARTAN_COLOR_BARS,
XTPG_BKGND_CROSS_HATCH,
XTPG_BKGND_RAINBOW_COLOR,
XTPG_BKGND_HV_RAMP,
XTPG_BKGND_CHECKER_BOARD,
XTPG_BKGND_PBRS,
XTPG_BKGND_DP_COLOR_RAMP,
XTPG_BKGND_DP_BW_VERTICAL_LINE,
XTPG_BKGND_DP_COLOR_SQUARE,
XTPG_BKGND_LAST

View solution in original post

0 Kudos
23 Replies
mkooli
Adventurer
Adventurer
5,655 Views
Registered: ‎04-14-2017

Hi @muzaffer  @avrumw ,

Any help please !

0 Kudos
mkooli
Adventurer
Adventurer
5,646 Views
Registered: ‎04-14-2017
0 Kudos
xud
Xilinx Employee
Xilinx Employee
5,574 Views
Registered: ‎08-02-2007

@mkooli Can you show me the VDMA GUI parameters and AXI4 Stream to Video Out IP GUI settings?

 

Please try to check "allow unaligned transfer" and set sync mode to none (free running) at VDMA read side. The other thing is use Master mode for Video Out IP, and then see if you can make it work. 

 

When AXI4-Stream to Video Out IP is in master mode, please dis-connect the connection of vtg_ce. In this situation, VTC is Video Master, which is in free running mode. if you use vtg_ce, it slows down the video timing coming from VTC, which can't be synchronous to the frame size of AXI4 Stream.

 

Also please confirm the frame size configured in VTC matches the ones in TPG. 

0 Kudos
mkooli
Adventurer
Adventurer
5,567 Views
Registered: ‎04-14-2017

Hi @xud,

Thanks for replying, ou find attached , the VDMA and "Axi to stream video out" setting :1.PNG

2.PNG

3.PNG

 

Yes the frame size is set the same in the TPG and VTC configuration  (800*600).

0 Kudos
xud
Xilinx Employee
Xilinx Employee
5,565 Views
Registered: ‎08-02-2007

@mkooli  I notice your timing mode for AXI4-Stream to Video Out IP is slave. As I mentioned please change it to master mode, and disconnect vtg_ce, and see if it makes difference.

 

For more details, please refer to page 23 and onwards of https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v4_0/pg044_v_axis_vid_out.pdf

 

As you can see, when there is VDMA in the Video Path, it's recommended to use master mode.

0 Kudos
mkooli
Adventurer
Adventurer
5,560 Views
Registered: ‎04-14-2017

@xud,

Ok I'm going to try the changes, thank you...

0 Kudos
mkooli
Adventurer
Adventurer
5,534 Views
Registered: ‎04-14-2017

HI @xud,

there is a little bit improve, i can display the frame (the tartan color bars)but when I execute each time gives me different results and sometimes the screen stays black,

What have I to verify ? does the frame size (800*600) can make a problem (must I reduce the size for example) ?

0 Kudos
xud
Xilinx Employee
Xilinx Employee
5,531 Views
Registered: ‎08-02-2007

How fast is your VTC and VTG clock?From your waveform screenshot, it looks like the read side is too fast. Can you use the same clock to drive clk of VTC and ap_clk of TPG? 

 

can you set genlock of read side to dynamic master?

0 Kudos
mkooli
Adventurer
Adventurer
5,522 Views
Registered: ‎04-14-2017

I solved the problem, just in my SDK code, I tryed to generate a color bars and a tartan color bars using this lines code each time:

 

XV_tpg_Set_bckgndId(&ptpg,XTPG_BKGND_COLOR_BARS);

XV_tpg_Set_bckgndId(&ptpg,XTPG_BKGND_TARTAN_COLOR_BARS);

 

I want to know if there is other frames form to test, if yes give me the line code please.

0 Kudos
xud
Xilinx Employee
Xilinx Employee
8,891 Views
Registered: ‎08-02-2007

@mkooli Glad to see you have resolved the problem. here are a list of patterns you can test with.

The software code is similar to COLOR_BARS and TARTAN. 

 

At HW side,  you need to ensure the associated options are checked in TPG GUI : 

XTPG_BKGND_H_RAMP = 1,
XTPG_BKGND_V_RAMP,
XTPG_BKGND_TEMPORAL_RAMP,
XTPG_BKGND_SOLID_RED,
XTPG_BKGND_SOLID_GREEN,
XTPG_BKGND_SOLID_BLUE,
XTPG_BKGND_SOLID_BLACK,
XTPG_BKGND_SOLID_WHITE,
XTPG_BKGND_COLOR_BARS,
XTPG_BKGND_ZONE_PLATE,
XTPG_BKGND_TARTAN_COLOR_BARS,
XTPG_BKGND_CROSS_HATCH,
XTPG_BKGND_RAINBOW_COLOR,
XTPG_BKGND_HV_RAMP,
XTPG_BKGND_CHECKER_BOARD,
XTPG_BKGND_PBRS,
XTPG_BKGND_DP_COLOR_RAMP,
XTPG_BKGND_DP_BW_VERTICAL_LINE,
XTPG_BKGND_DP_COLOR_SQUARE,
XTPG_BKGND_LAST

View solution in original post

0 Kudos
mkooli
Adventurer
Adventurer
5,798 Views
Registered: ‎04-14-2017

Hi @xud,

I want to know if I can display the Test Pattern Generator frames using a HDMI output (instead od VGA), if yes where can I find the SDK code for the ZedHDMI (I have a problem with that but the design I did it).

Thanks

0 Kudos
xud
Xilinx Employee
Xilinx Employee
5,763 Views
Registered: ‎08-02-2007

@mkooli Yes you can, but TPG doesn't generate audio, you don't hear any sound. HDMI is compatible with DVI, so it can be displayed using HDMI. What's ZedHDMI? 

0 Kudos
mkooli
Adventurer
Adventurer
5,759 Views
Registered: ‎04-14-2017

Hi @xud,

ZedHdmi is HDMI for the Zedboard card, thanks for replaying.

0 Kudos
xud
Xilinx Employee
Xilinx Employee
5,747 Views
Registered: ‎08-02-2007

Sorry - I don't have Zedboard user guide, but if you have it. You need to double check whether ADV7511(or another HDMI codec) is wired to support YCbCr 4:2:2 or YCbCr 4:4:4, and then you need to change two things :

1. the color format in AXI4 Stream to Video Out IP

2. the associated register value in software driver. Different board has different settings. 0x16 register of ADV7511 is used to set the output color format. 

 

0 Kudos
mkooli
Adventurer
Adventurer
5,720 Views
Registered: ‎04-14-2017

Hi @xud,

Why should I change the format AXI4 Stream to Video Out IP  ,doesn't the HDMI support the RGB format ?

In my project, is it possible to display TPG frames with both HDMI and VGA at the same time ?

0 Kudos
xud
Xilinx Employee
Xilinx Employee
5,716 Views
Registered: ‎08-02-2007

From the Zedboard Schematic, ADV7511 only supports YUV4:2:2 : 

http://zedboard.org/sites/default/files/documentations/ZedBoard_RevD.2_Schematic_130516.pdf

 

I'm not sure above revision is the same as what you have. Unfortunately this is designed on board, You can use Color-Space Converter IP, and chroma resampler IP to convert RGB to YUV4:2:2.

 

Then you can have two interfaces : One RGB, and the other YUV4:2:2 (driven to HDMI)

0 Kudos
mkooli
Adventurer
Adventurer
5,679 Views
Registered: ‎04-14-2017

Hi @xud,

I tryed all what ou advice me to do but the project still not working, you will find attached my design, the zed_hdmi_disply which probably have the problem, the axi_video_out configuration and the chroma resampler block,

Please tell me what must I verify (also maybe the VTC has connection problems).

 

1.PNG

2.PNG

3.PNG

 

4.PNG

 

0 Kudos
xud
Xilinx Employee
Xilinx Employee
5,672 Views
Registered: ‎08-02-2007

Firstly the component width should be 8 for Zedboard. Can you get lock signal of AXI Stream to Video Out asserted? If so, the issue is at software side. 

mkooli
Adventurer
Adventurer
5,571 Views
Registered: ‎04-14-2017

Hi @xud

the component widh that shoud be 8 is about the "chroma resampler" or the "axi video out" ?

No, I'm certain that my SDK code is correct, the problem is in the design, especially in the vtc connection pin and also in setting the clocks frequency.

0 Kudos
xud
Xilinx Employee
Xilinx Employee
4,229 Views
Registered: ‎08-02-2007

From the Zedboard schematic, the hdmi data width is 16bits, that's why I think it should be 8 bpc.

0 Kudos
mkooli
Adventurer
Adventurer
4,227 Views
Registered: ‎04-14-2017

ok thanks

0 Kudos
mkooli
Adventurer
Adventurer
4,226 Views
Registered: ‎04-14-2017

just have an idea about the clocks, what value must I assign for the VTC, the clk0 and clk2 of the processor ?

0 Kudos
mkooli
Adventurer
Adventurer
4,201 Views
Registered: ‎04-14-2017

Hi @xud

I have a problem with making connection between the TPG and the Zedhdmi_display, I want to know if you can prvide me with an example of a block design showing connection between those IP blocks.

Regards.

0 Kudos