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Visitor
Visitor
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Registered: ‎07-17-2018

VDMA reset recovery timing violation

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I have a single reset recovery timing violation located within the AXI VDMA IP (version 6.3, in Vivado 2017.4). My S2MM AXIS slave clock is 85 MHz and S2MM AXI master clock is 100 MHz. The violation is a result of a reset on a FIFO that uses the 100MHz clock being driven by a flop clocked at 85MHz.

Is it safe to set_false_path to ignore this timing violation?

 

NameSlackLevelsRoutesHigh FanoutFromToTotal DelayLogic DelayNet DelayRequirementSource ClockDestination ClockException
Path 445-1.54123[x]/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.wr_rst_reg_reg/C[x]/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST1.050.400.651.95bclk_85_[x]bclk_100_[x] 

 

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Moderator
Moderator
531 Views
Registered: ‎11-09-2015

Hi @banschu 

As you are working on 7-series you might want to check the following AR:

https://www.xilinx.com/support/answers/71984.html

There are missing constraints for the VDMA when the stream and Memory mapped interfaces are using different clocks.

You might want to use 2019.1 to avoid this issue (or use the constraints mentioned in the AR).

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
541 Views
Registered: ‎10-04-2017

Hi @banschu,

 

I would not recommend setting a false path. I don't know enough about the internal logic of the FIFO36 to know if this will be an issue or not.

 

However, this should not be an issue in the first place. Are you in 7-Series, US or US+?

If you open up a schematic and select the FIFO, in the Cell Properties menu, is the FIFO set so Synchronous or Asynchronous?

In 7 series, this is the DO_REG (UG743)

In US/US+, this is CLOCK_DOMAINS (UG573/UG974)

 

I am guessing that for some reason this is set to Synchronous in your system. 

 

-Sam

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Visitor
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Registered: ‎07-17-2018

Hello @samk 

This is 7-Series logic (Zynq). The FIFO appears to bet set as Asynchronous. DO_REG=1, but I think you want to know EN_SYN=false.

image.png

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @banschu 

As you are working on 7-series you might want to check the following AR:

https://www.xilinx.com/support/answers/71984.html

There are missing constraints for the VDMA when the stream and Memory mapped interfaces are using different clocks.

You might want to use 2019.1 to avoid this issue (or use the constraints mentioned in the AR).

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

Moderator
Moderator
525 Views
Registered: ‎10-04-2017

Hi @banschu,

 

Thank you for checking, it looks like Florent found an AR that addresses the issue, and it looks like a false path will solve the problem.

Regards,

Sam

 

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