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Adventurer
Adventurer
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Registered: ‎06-20-2019

VDMA tready signal goes low after a few transactions

Hi,

I am trying to use VDMA in my design and I am feeding it with a valid supplier. I configure VDMA's register's in accordance with the "General Use Cases" part of the document PG020. After writing to the register, I am reading them and I can observe that data are written properly. After configuring and writing to the VSIZE registers, the streams are flowing. However, s_axis_s2mm_tready goes low after getting the first line. After getting the second tuser hit for the next line, it goes low and you can see this in the picture provided below. I set s_axis_s2mm_tkeep to 1 and f values but nothing has changed. What am I supposed to do?

Thank you for your valuable time.

 

Selection_192.png
Selection_193.png
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @yhy.xilinx 

Debugging tips:

  • Look at the status register and check that there is no error flagged. This is something I have mentioned in the following blog article:
    Video Series 25: Debugging issues on the AXI VDMA IP
  • Check the memory interface as well. If the memory interface is stalled, then it will stall the AXI4-Stream interface

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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