03-26-2018 08:52 PM
Going through the documentation of both IP core, it seems these two cores functionality is overlapping. In our video application we wish to just buffer and push the video into DDR ram. Is it fair to assume that FrameBuffer Write is all we need? When do we need a full VDMA core?
04-05-2018 07:56 AM
03-28-2018 09:21 AM
04-04-2018 12:51 AM
If everything is clear for you, please kindly close the topic by marking a reply as accepted solution.
Thanks and Regards,
04-05-2018 04:31 AM
Thanks for the reply!
I have started using Video Frame Buffer instead of the VDMA, besides being a bit awkward. For instance, I had to pad the stream since for YUV422 it still expects 3x(8bits) components while my Video In to AXI4 spits outs 2x(8bits), this was clearly documented so no big deal.
One thing I noticed is that in terms of utilization it is using 2x DSP slices while VDMA uses none...I am wondering why would one need this for this function? I see the HLS logo on the actual block design and I was wondering if one had access to the (C/C++?) source code of the IP core ... (perhaps not!).
Anyways my design is quite heavy on the use of DSPs and It may happen that I will revert back to using VDMA...
Any views on this?
04-05-2018 07:56 AM
08-12-2019 09:33 PM
So, Can i use Video FrameBuffer with Zynq-7000? If yes, can you show me how?
I trying to use Video FrameBuffer Read + Video Mixer to driven ALI3 10inch from Avnet, built with Petalinux, xilinx drm driver initialize ok but I can't see any /dev/fbx on root file system.
Can you give me some suggestion for this?
Thanks and best regard,
10-21-2020 04:21 AM
I am pretty new to this concept . can someone explain me when to use VDMA and when to use frame buffer write ?
So , what i understood is that we use VDMA when we have to support live streaming interface.
and Support VDMA when simply store data in to DDR memory .
if someone has more details please share.
10-21-2020 05:07 AM
You might want to refer to the following AR as this is covering it: