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Nikhil_Thapa
Explorer
Explorer
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Registered: ‎05-28-2020

VDMA writes only few pixel data of video frame

Hello Everyone,

I am making such a Microblaze design using Vivado 2019.2, where I am taking 16 bit monochrome data from CCD camera and I am using Video In to AXI4 Stream IP to convert monochrome data into AXI4 Stream and finally, I am using VDMA IP to write data into DDR memory. To write data in 32 bit format, I am making 16 bit data to 32 bit data (4 Bytes) by padding 16 zeros, that is, 16'b0, tdata[15:0] by using subset converter IP.

For clocking information, I am feeding 200 MHz clock to m_axi_s2mm_aclk and s_axis_s2mm_aclk pins of VMDA IP and I am also feeding 200MHz clock to sys_clk_i pin of MIG 7 Series IP whereas CCD camera is giving 10MHz pixel clock.

Well, when I ran this design, I got design working. However, when I read the memory to check whether camera data were written into memory or not, I found that only the first line of video frame was written into the memory. Meaning, CCD camera was giving 648x480 video frame but only 648 pixel (first line) data were always found to be written into memory. I initially doubted that CCD camera was sending first line pixel data but later on, I used ILA and found that camera was giving data correctly and pixel clock was also correct.

I am stuck here. Could somebody point out the reason behind this? I would go through it to check in my design. I would be very grateful.

I have included all the necessary information below.

IP CustomizationIP CustomizationVDMA IP customizationVDMA IP customizationScreenshot of memory readingScreenshot of memory readingVDMA Configuration code snippetVDMA Configuration code snippet

 

Thanks,

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florentw
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Registered: ‎11-09-2015

HI @Nikhil_Thapa 

Did you try to disable the cache to make sure you were not reading from it?

Is the AXI VDMA still running? You might want to check the following article Video Series 25: Debugging issues on the AXI VDMA IP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Nikhil_Thapa
Explorer
Explorer
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Registered: ‎05-28-2020

Hi @florentw,

Thanks for reply.

And yes, I used  Xil_DCacheDisable() in the main function to disable the data cache. But the memory data status remained just the same. By the way for the information, I used XSCT command to read the memory contents.

And I also followed the VDMA debugging video series and I did this;

XSCT Memory read write commandXSCT Memory read write command

This looks like same thing as in the video series. However, I also got 12 and 14 bit high.

Status register bit valueStatus register bit value

I checked the VSIZE and HSIZE configuration. They looked good. But still getting same status value.

Could you please suggest me other points to check?

 

Thank You !

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florentw
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Moderator
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Registered: ‎11-09-2015

HI @Nikhil_Thapa 

You need to fix the error from the VDMA. 

It seems that there is an error accessing the memory, so you might want to add an ILA on the AXI MM interface and check what is happening there


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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