VPPS deinterlacer CDMA stall

[pierlum]

Hello I'm working with Vivado 2018.2 and VPSS in deinterlacer mode only. I have a strange problem. I have a 1Gbyte DDR3 mapped on axi from 0x80000000 to 0xBFFFFFFF. I selected for VPSS a FrameBufBaseaddr of 0x80000000 and i started VPSS. With CDMA I access DDR3 in the interval 0x90000000-0xBFFFFFFF. If CDMA read from DDR3 (DDR3->BRAM) I have no problem, but if CDMA write to DDR3 (BRAM->DDR3) on the first write CDMA stall (CDMA status register at 0 indefinitely). If I disable VPSS, CDMA works properly. If I select 0xC0000000 (not axi mapped) as FrameBufBaseaddr CDMA works properly. So it seems that VPSS takes upon all DDR3 and doesn't allow other peripherals to write on it. Am I doing something wrong?

Thank you in advance for the help.

[florentw]

Hi @pierlum,

You can try to change which part of the memory the VPSS can see (and access) in the address editor. This way you can be sure you are not overlapping

[pierlum]

Hi @florentw,

how can do this without have critical warnin? If for example VPSS maps DDR3 from 0x80000000 to 0x8FFFFFFF (256 MByte) and CDMA maps DDR3 from 0x80000000 to 0xBFFFFFFF (1GByte) I have critical warning for different address range. Is there another way to do what you suggested me? Thank you very much.

[florentw]

HI @pierlum,

Did you try VPSS maps DDR3 from 0x80000000 to 0x8FFFFFFF and CDMA maps DDR3 from 0x90000000 to 0xBFFFFFFF?

[florentw]

Hi @pierlum,

Do you have any updates on this?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" buton below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,

[pierlum]

Hi @ florentw,

mapping DDR3 from 0x90000000 to 0xBFFFFFFF I have error : "misaligned address". Thanks for the help.

[florentw]

HI @pierlum,

Where do you get the misaligned error? Is it in the address editor tab?

[pierlum]

Hi @florentw,

I got error changing address in address editor tab.

Thank you.

[florentw]

Hi @pierlum,

You might need to reduce the size of the memory you are targetting.

[pierlum]

Hi @florentw,

thank you for the help. Maybe I could solve my problem if it was possible to virtually split 1Gbyte DDR3 in AXI4 domain and map it on two different 512 MByte address space. Could it be possible to this in Vivado? Thank you.

[florentw]

Hi @pierlum,

Yes this is done in the tab editor... This is actually what I was already trying to suggest with my previous replies...

[pierlum]

Hi @florentw,

Thank you very much. I have done this now in address editor following your advices and now Vivado is running implementation. I have only the critical warning in picture attached. It is safe to ignore it? Thank you.

Edit:

Unfortunately this solution doesn't work. Probably VPSS would need of a dedicated memory.or maybe some AXI4-MM fifo palced opportunely.