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Participant
Participant
872 Views
Registered: ‎04-23-2018

VPSS example design without DMA

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Hi,

Is there any example design for KCU105/ZCU102 (preferably ) which uses VPSS (Video Processing subsystem) without DMA / frame buffer enabled?

I refered to https://www.xilinx.com/support/documentation/application_notes/xapp1291-video-subsystem.pdf example design

I understand that DMA is required for supporting Interlaced video. Currently I am working with Progressive video inputs only.

I created the design in kCU105 with HDMI in & out using VPSS and the design is working with DMA enabled in VPSS. As our design has critical DDR4 bandwidth requirement, we want to avoid DDR bandwidth usage for VPSS. So, I disabled the DMA inside VPSS and commented the "XVprocSs_SetFrameBufBaseaddr" in sdk.

With Regards,

Hariprasad Bhat

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Moderator
Moderator
771 Views
Registered: ‎11-09-2015

Hi @hariprasadb,

In the current version of vivado (2018.3) you can generate the VPSS example design for a specific configuration. For example you should be able to generate it in chroma ressampler only. This shouldn't use the DMA.

To generate the example design, refer to PG231 chapter 5.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Teacher
Teacher
839 Views
Registered: ‎06-16-2013

Hi @hariprasadb

 

What resolution and frame rate do you support ?

It depends on this answer wheter you can do it or not.

 

Best regards,

 

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Participant
Participant
821 Views
Registered: ‎04-23-2018

Hi @watari,

Currently I am targetting for full hd 1080P @60Hz wuth HDMI RX and TX subsystems.

HDMI RX SS(FHD 60HZ) -> VPSS (RGB to YCBCR) -> HDMI TX SS (FHD 60HZ).

Once this is done, we are planning 720@60Hz, 1080P@30Hz as well.

With Regards,

Hariprasad Bhat

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Teacher
Teacher
800 Views
Registered: ‎06-16-2013

Hi @hariprasadb

 

It's wasy way to use a lerge FIFO as line buffer or AXI4Stream IP (Video in to AXI4Stream and AXI4Stream to Video out).

 

Would you consider them ?

 

Best regards,

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Moderator
Moderator
772 Views
Registered: ‎11-09-2015

Hi @hariprasadb,

In the current version of vivado (2018.3) you can generate the VPSS example design for a specific configuration. For example you should be able to generate it in chroma ressampler only. This shouldn't use the DMA.

To generate the example design, refer to PG231 chapter 5.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Moderator
Moderator
735 Views
Registered: ‎11-09-2015

Hi @hariprasadb ,

Do you have any updates on this?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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