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Observer
Observer
590 Views
Registered: ‎07-18-2019

VPSS into Video Mixer does not work

My design consist in two video streams being downscaled and mixed into a single output video stream. I am using VPSS in scaler only mode, and a Video Mixer block.

When I try to feed the downscaled VPSS output in the Video Mixer, both the VPSS and Mixer stop.

I tried to replace the VPSSs with TPGs with the same resolution and color format and the Mixer works fine. At the same time each VPSS works fine if it is not fed into the Mixer. I suspect it could be due to some kind of synchronization error, as I read that the Video Mixer does not perform synchronization itself.

If so, how can I fix this?

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Moderator
Moderator
569 Views
Registered: ‎11-09-2015

Hi @giacomo.gloria 

What vivado version are you using? Are you running under linux or baremetal?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
560 Views
Registered: ‎07-18-2019

I am using vivado 2019.1 on a KC705 atm.

 

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Moderator
Moderator
558 Views
Registered: ‎11-09-2015

Hi @giacomo.gloria 

Are you running under linux or baremetal?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
548 Views
Registered: ‎07-18-2019

Baremetal

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Moderator
Moderator
534 Views
Registered: ‎11-09-2015

Hi @giacomo.gloria 

could you get an ILA capture of the AXI4-Stream interface between the VPSS and the Video Mixer? I would like to see which IP is waiting on the other to be ready.

Thanks


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
456 Views
Registered: ‎07-18-2019

Mixer deasserts TReady shortly after the start of the first output frame from VPSS. Seems like a backpressure issue to me.

Here it is a screenshot from the ILA core

vpss_ila0_0.jpg

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Adding AXI4 Stream FIFOs seems to allow a few lines to get through, just to stall in the exact same way.

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Moderator
Moderator
437 Views
Registered: ‎11-09-2015

Hi @giacomo.gloria 

It seems indeed to be a back pressure issue. The difference you see with the test pattern generator and the VPSS is that the TPG will continuously generates data. While the VPSS is a slave of the input video stream.

So I would check your input video stream. If the input is not fast enough to generate the output maybe you should consider adding a VDMA or Video Frame buffer (before or after the VPSS) to store full frames. This would allow to have frames repeated if the input is not fast enough to provide enough input.

Because if you are doing up-scaling, you need to have the output faster than the input


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
426 Views
Registered: ‎07-18-2019

Thank you for your reply.

At the moment my video chain is TPG => VPSS => Video Mixer, so I expected the TPG to handle the backpressure. Apparently this is not the case. Anyway my design has a different video input, so I will need to take care of the issue eventually. I looked into frame buffers, but they apparently either have a Memory mapped input or output. Am I forced to move away from the AXI4 stream interface if I want to use them?

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Moderator
Moderator
420 Views
Registered: ‎11-09-2015

HI @giacomo.gloria 


@giacomo.gloria wrote:

Thank you for your reply.

At the moment my video chain is TPG => VPSS => Video Mixer, so I expected the TPG to handle the backpressure. Apparently this is not the case.

[Florent] - The VPSS will probably add some latency as well. You might want to try to increase the frequency of both the TPG and the VPSS (or at least the VPSS)

Anyway my design has a different video input, so I will need to take care of the issue eventually. I looked into frame buffers, but they apparently either have a Memory mapped input or output. Am I forced to move away from the AXI4 stream interface if I want to use them?


[Florent] - The AXI VDMA or Video Frame buffer are used to interface a memory so they have an AXI-MM interface. However, if you have both a write and read side, at the end your pipeline will be from AXI4-Stream to AXI4-Stream

                                                                             Memory

                                                                            |             |            

AXI4-S ---> Vid Frame buffer WR > AXI4-MM-->|             |---> AXI4-MM > Vid Frame buffer RD --> AXI4-S


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
411 Views
Registered: ‎07-18-2019

I see. I'll try to work on frequency and see how the VPSS handles it.

Is there some different approach I can take? It will probably be impossible to access memory in the final project...

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Moderator
Moderator
407 Views
Registered: ‎11-09-2015

Hi @giacomo.gloria 

If this is the VPSS which is not producing the data fast enough, increasing the frequency or the number of pixel per clock can help.

But if this is your input data which is not fast enough this might be more complicated. A big FIFO can help. But the advantage of having the frame stored in memory is that you can repeat it if needed


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
199 Views
Registered: ‎11-21-2018

Hi @giacomo.gloria 

Is this issue resolved?

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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