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jiaohuang2004
Observer
Observer
358 Views
Registered: ‎09-22-2020

Vid out cannot be locked

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When VTC generates timing automatically, vidout can be locked!It works well!Video cannot be locked when VTC uses external frame trigger mode.Just add external trigger signal to VTC, vidout can't work, it has no output.

Who can solve my problem?Thanks!

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jiaohuang2004
Observer
Observer
206 Views
Registered: ‎09-22-2020

Thank you for your reply!
Yes,I think you're right.Because there is no error when VTC is running freely, and the problem occurs only after external trigger.
The trigger signal enters through the zynq pin. As shown in the picture below.
I detect the rising edge of the trigger signal, then access VDMA, and delay for a period of time to enter VTC.
Can you give me some advice?
In addition:Pclk =36MHz,Trigger signal = 30Hz

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7 Replies
trevorr
Xilinx Employee
Xilinx Employee
317 Views
Registered: ‎09-09-2020

Hi @jiaohuang2004 ,

 

Could you provide more information on the source of the fsync_in signal?

 

This is likely the source of the issue. 

 

Regards, 

 

Trevor Rishavy

Xilinx Product Application Engineer

 

watari
Teacher
Teacher
302 Views
Registered: ‎06-16-2013

Hi @jiaohuang2004 

 

Would you refer this post ?

 

https://forums.xilinx.com/t5/Video-and-Audio/AXI4-Stream-to-Video-Out/td-p/1227495

 

Also, you can find the reason when you make sure status signal on AXI4 Stream to Video Out IP.

Would you make sure status signal ?

Refer this url, if you want to know detail.

 

https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v4_0/pg044_v_axis_vid_out.pdf#page=11

 

Best regards,

jiaohuang2004
Observer
Observer
250 Views
Registered: ‎09-22-2020

Thanks for your reply

I can't open it.It was created by vivado 2018.1, and my version is vivado2019.1

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jiaohuang2004
Observer
Observer
248 Views
Registered: ‎09-22-2020

Can you tell me how to open it with vivado2019.1?Thanks

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jiaohuang2004
Observer
Observer
241 Views
Registered: ‎09-22-2020

Thank you for your reply!
Yes,I think you're right.Because there is no error when VTC is running freely, and the problem occurs only after external trigger.
The trigger signal enters through the zynq pin. As shown in the picture below.
I detect the rising edge of the trigger signal, then access VDMA, and delay for a period of time to enter VTC.
Can you give me some advice?
In addition:Pclk =36MHz,Trigger signal = 30Hz

截图02.png
截图04.png
截图05.png
截图03.png
0 Kudos
jiaohuang2004
Observer
Observer
210 Views
Registered: ‎09-22-2020

locked=0

截图06.png
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jiaohuang2004
Observer
Observer
207 Views
Registered: ‎09-22-2020

Thank you for your reply!
Yes,I think you're right.Because there is no error when VTC is running freely, and the problem occurs only after external trigger.
The trigger signal enters through the zynq pin. As shown in the picture below.
I detect the rising edge of the trigger signal, then access VDMA, and delay for a period of time to enter VTC.
Can you give me some advice?
In addition:Pclk =36MHz,Trigger signal = 30Hz

View solution in original post

截图02.png
截图04.png
截图03.png
0 Kudos