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Registered: ‎11-09-2015

Video Beginner Series 15: Creating a Pattern Generator using HLS (Part 2)




This Video Beginner Series 15 is a continuation of the shows Video Beginner Series 14 how to create a Video Pattern Generator IP for Vivado from C++ code using Vivado HLS. In the Video Beginner Series 14, the Video Pattern Generator was created using C++ and validated using HLS Open CV library. In this tutorial will convert to RTL (Verilog or VHDL) using Vivado HLS.



Reminder on User Guides to understand HLS. The main docs are UG998 - Introduction to FPGA Design with Vivado High-Level Synthesis, UG902 - Vivado Design Suite User Guide - High-Level Synthesis and UG871 - Vivado Design Suite Tutorial - High-Level Synthesis.


Note: This video series assumes that you have some knowledge in C/C++ coding.



 1. Tutorial – Creating a Pattern Generator using Vivado HLS (part 2)
2. What Next?


Tutorial – Creating a Pattern Generator using Vivado HLS (part 2)


Note 1: This tutorial is intended to be used only with Vivado 2018.1

Open the Vivado HLS project

  1. Download the tutorial files and unzip the folder

  2. Open Vivado HLS 2018.1

  3. Click on Open Project

  4. Open the project Video_Pattern_Generator from the unzipped folder

This is the project which was created for the Xilinx Video Series 14 with the C++ code completed.

Run C Synthesis

  1. Run C Synthesis by clicking on Solution > Run C Synthesis > Active Solution

A synthesis report will open. We can analyze it.

  • Performance Estimate

If we look at the performance estimates section, we can see that the latency number is big (481201)

However, this number is the time to execute the function one time. But the function will generate one full image. The image size is defined in the header file (video_pattern_generator.h). The height is 600 and the width 800. This means that 480,000 pixels need to be generated. Thus the actual latency between two frames would be 1201 clock cycle. We can ignore this for the moment


  • Utilization Estimates

This section shows the FPGA resources which should be used by the FPGA to implement the IP. This might change during synthesis of the full design. For this Video Series we will not look at this.


  • Interface

In this section we can see what interfaces have been implemented in the core



We can see some signals starting by ap_*. These signals are used to control the IP. We will keep them.

For the m_axis_video_* interface, we can see that the tool did not infer an AXI4S interface but created multiple interfaces (protocol ap_fifo), one for each signal.

This is because we haven’t told the tool that we want this interface to be an AXI4-Stream interface.


Improve the core

  1. Open the source file (video_pattern_generator.cpp)

  2. Find the directive window and right click on m_axis_video and click Insert Directive …


  1. In the Vivado HLS Directive Editor, configure as follow
    • Directive: Interface
    • Destination: Source File
    • Mode: axis



  1. We can then see that a directive was added by the tool into the source file

This is telling the synthesis tool that we want the m_axis_video interface to be an AXI4-Stream interface.


  1. Save the source file and run C Synthesis

  2. In the Synthesis summary, we can see that the tool has now successfully created an AXI4-Stream interface (protocol axis)



  1. However, if we look at the latency, it has doubled.


To improve the latency, we can try to pipeline the for loops.

  1. Open the source file (video_pattern_generator.cpp)

  2. In the Directive window, right click on the first for loop and click Insert Directive…



  1. In the Vivado HLS Directive Editor, configure as follow
    • Directive: Pipeline
    • Destination: Source File




    1. We can see that the tool adds a directive under the for loop.


Note: This directive will apply to the sub-loop


  1. Run C Synthesis

  2. If we check the latency again, it is down to a number close to the number of pixels to output.

  3. We can now export the IP to test it in Vivado. Click on Solution > Export RTL or click on the icon 11.png

  4. In the Export RTL as IP window, leave the default settings and click OK


  1. Close Vivado HLS


Test the IP in Vivado Simulation

The IP was exported to <XVES_0015>\Video_Pattern_Generator\solution1\impl\ip.

  1. Copy the zip file to <XVES_0015>\src\ip_repo and extract it.

  2. Open Vivado 2018.1

  3. In the tcl console, cd into the Video Series main directory (cd <path>/XVES_0015)

  4. In the tcl console, source the script tcl (source ./create_proj.tcl)

  5. This creates a new project with our new HLS IP connected in the BD


  1. Launch the simulation and run it for 14 ms

  2. When the simulation is finished, open the generated image XVES_0015\proj_1\proj_1.sim\sim_1\behav\xsim\image_out_1.ppm with GIMP. We can see that we get the expected red pattern.




What Next?


  • Do you have issues/questions following this Vivado Beginner Series?
    1. Search on the Xilinx forums for similar questions
    2. Create a new topic on the HLS Board or Video Board for your issue/question with the title starting with [Video Beginner Series 15] and followed by a quick description of your issue/question


  • You liked this Video Series?
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Product Application Engineer - Xilinx Technical Support EMEA
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