10-10-2018 12:16 AM - edited 11-13-2018 08:09 AM
This Video Beginner Series 15 is a continuation of the shows Video Beginner Series 14 how to create a Video Pattern Generator IP for Vivado from C++ code using Vivado HLS. In the Video Beginner Series 14, the Video Pattern Generator was created using C++ and validated using HLS Open CV library. In this tutorial will convert to RTL (Verilog or VHDL) using Vivado HLS.
Reminder on User Guides to understand HLS. The main docs are UG998 - Introduction to FPGA Design with Vivado High-Level Synthesis, UG902 - Vivado Design Suite User Guide - High-Level Synthesis and UG871 - Vivado Design Suite Tutorial - High-Level Synthesis.
Note: This video series assumes that you have some knowledge in C/C++ coding.
Note 1: This tutorial is intended to be used only with Vivado 2018.1
This is the project which was created for the Xilinx Video Series 14 with the C++ code completed.
A synthesis report will open. We can analyze it.
If we look at the performance estimates section, we can see that the latency number is big (481201)
However, this number is the time to execute the function one time. But the function will generate one full image. The image size is defined in the header file (video_pattern_generator.h). The height is 600 and the width 800. This means that 480,000 pixels need to be generated. Thus the actual latency between two frames would be 1201 clock cycle. We can ignore this for the moment
This section shows the FPGA resources which should be used by the FPGA to implement the IP. This might change during synthesis of the full design. For this Video Series we will not look at this.
In this section we can see what interfaces have been implemented in the core
We can see some signals starting by ap_*. These signals are used to control the IP. We will keep them.
For the m_axis_video_* interface, we can see that the tool did not infer an AXI4S interface but created multiple interfaces (protocol ap_fifo), one for each signal.
This is because we haven’t told the tool that we want this interface to be an AXI4-Stream interface.
This is telling the synthesis tool that we want the m_axis_video interface to be an AXI4-Stream interface.
To improve the latency, we can try to pipeline the for loops.
Note: This directive will apply to the sub-loop
The IP was exported to <XVES_0015>\Video_Pattern_Generator\solution1\impl\ip.