11-14-2018 01:40 AM - edited 11-14-2018 01:43 AM
This Video Beginner Series 18 is a continuation of the Video Beginner Series 17. In this series we will test the Video Crop IP generated with Vivado HLS in RTL simulation with Vivado. We will use the test pattern generator as input stimuli and we will write the output to an image file.
Note: This tutorial is intended to be used only with Vivado 2018.1
Note: A valid license for the Test Pattern Generator is required to build the design.
The design is based on the Xilinx Video Series 5.
Note: The IP generated by HLS was extracted in the src/ip_repo directory and this directory has been added to the repository in Vivado. Refer to section Test the IP in Vivado Simulation of the Xilinx Video series 16 for information on these steps.
Expend the m_axis_video interface of the video crop and connect the pins TVALID, TREADY, TDATA, TLAST, TUSER and TVALID to the corresponding BD’s port.
Validate the BD, you should get no error. Save the BD
Image written Configured and output resolution match, test succeeded
This looks promising as the output size is as expected
We can see that we get a nice pattern and that the image size is 320x480. In the test bench, the TPG was configured to output 640x480 thus everything looks correct.
We can see from the TDATA and TVALID output signals from the TPG and from the Video Crop that the video crop seems to correctly output only half of the image. Thus, everything looks also good.
We can notice that the IP keeps sending the tdata and tlast signals for the second half of the image. This is correct according to the AXI4-Stream specification. As tvalid is low, the other signals are not “transmitted” (thus they can take any value).